教師著作
Permanent URI for this collectionhttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/31276
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Item Top-Down Placement for Hierarchical Layout System(1986-08-01) 張國恩; 馮武雄; Chang, Kuo-En; Feng, Wu-ShiungItem A new dynamic switch-box router(1987-12-01) 張國恩; 馮武雄; Chang, Kuo-En; Feng Wu-ShiungItem The Topological Order Determination for Three-Layer Channel Routing Problem(1988-01-01) 張國恩; Lai, T. H.; 馮武雄; Chang, Kuo-En; Lai, T. H.; Feng Wu-ShiungItem The pin alignment in VLSI routing with movable terminals(1989-01-01) 張國恩; 馮武雄; Yu, H. J.; Chang, Kuo-En; Feng Wu-Shiung; Yu, H. J.Item Constrained via minimization for three-layer routing(Elsevier, 1989-07-01) Chang, K. E.; Jyu, H. F.; Feng, W. S.The previous constrained via minimization problem for VLSI previous three-layer routing is the problem of deining which previous layers can be used for previous routing the wire segments in the interconnections of nets so that the number of previous vias is minimized. This problem has been shown to be NP-complete15. In this paper, this problem is first transformed to the contractibility problem of a previous three -colourable graph, then an heuristic algorithm is proposed on the basis of the graph contractability model. From experimental results, the algorithm proves faster and more efficient at generating very good results. For a typical case, the number of previous vias can be reduced by about 30%.Item 有關VLSI佈局層指定的圖形縮減問題(中國工程師學會, 1989-07-01) 張國恩; 鞠鴻飛; 馮武雄; Chang, K. E.; Jyu, H. F.; Feng, W. S.Item An efficient layer assignment for three-layer VLSI routing(1989-09-01) 張國恩; 馮武雄; Fang, S. C.; Chang, Kuo-En; Feng Wu-Shiung; Fang, Sung-ChuanItem On Transformation of Logic Specifications into Procedural Programs(IEEE, 1989-10-23) Lin, Janet Mei-Chuen; Juang, Jie-Yong; Yau, Stephen SA method for transforming a source program expressed as a set of Horn clauses into a target program in an Algol-like procedural language is presented. Compared with deterministic execution of a conventional program, the top-down procedural interpretation of a Horn clause program is inherently nondeterministic. This transformation method is aimed at removing certain types of nondeterministic in a Horn clause program via a variable-dependence analysis and a procedure formation scheme. It is assumed that the input/output mode information for each predicate in the Horn clause is known in advance and that each predicate is used unidirectionally, i.e. each argument in the argument list of a predicate is used either as an input or an output, but not both. Therefore, the Horn clauses treated by this method represent only a subclass of the general Horn logic clauses. During the transformation process, the method is also capable of discovering inconsistent or missing information in the source program.Item 神經網路(國立台灣師範大學, 1990-04-01) 張國恩Item Maximizing pin alignment in VLSI routing(中國工程師學會, 1990-05-01) 張國恩; 馮武雄; Chang, Kuo-En; Feng, Wu-ShiungItem Via minimization with associated constraints in three-layer routing problem(1990-05-01) Fang, Sung-Chuan; Chang, Kuo-En; Feng, Wu-ShiungVia minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results.Item A delayed layering three-layer channel routing(Institution of Engineering and Technology, 1990-07-01) Chang, K. E.; Feng, W. S.A new three-layer channel router with 'delayed layering' technique is presented. The delayed layering scheme in the routing can improve the capability of the router to reach comprehensive objectives. This new router not only minimises the tracks used, but also minimises the via usage and maximises the use of preferred routing layers. The delayed layering router consists of two steps: track assignment and layer assignment. The track assignment uses a topological sorting algorithm to determine the horizontal track number of every net. A layerless layout will result from the track assignment. The layer assignment heuristically determines which layers can be used for routing the wire segments in the layerless layout, such that the vias generated are as small as possible. The experiments showed that the solution quality with respect to via usage was better than the previous solutions and the number of tracks used in channel was satisfactory.Item 三層通道佈線的拓樸排序分類演算法(中國工程師學會, 1990-11-01) 張國恩; 賴廷樺; 馮武雄; Chang, K. E.; Lai, T. H.; Feng, W. S.Item Issues on Deterministic Transformation of Logic-Based Program Specification(IEEE, 1990-11-06) Lin, Janet Mei-ChuenIssues of logic-based program transformation are discussed, and a method for transforming a source program expressed as a set of extended Horn clauses into a target program in an Algol-like procedural language is presented. The potential applications of this transformation method include (1) automatic synthesis of programs from design specifications which are either written in or translatable into extended Horn logic clauses, (2) adaptation of existing logic programs to a procedural execution environment in order to improve execution efficiency or facilitate reusability of the software, and (3) support of a hybrid-programming environment.Item A new hybrid sense algorithm for three-layer via minimization with practical constraints(1990-12-01) Fang, Sung-Chuan; Chang, Kuo-En; Feng, Wu-ShiungItem Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems(1991-03-01) Fang, Sung-Chuan; Chang, Kuo-En; Feng, Wu-Shiung; Chen, Sao-JieItem 以神經網路處理佈線問題(中國工程師學會, 1991-05-01) 施保旭; 馮武雄; 張國恩; Shih, P. H.; Feng, W. S.; Chang, K. E.在VLSI佈局中，佈線問題是一個很重要的部份，其工作在於將給定的連線要求予以正確的完成。此問題已被證明為 NP －完全性問題。目前所見的方法大多是採用啟發式的演算法。 本論文提出一套植基於 Hopfield and Tank 模型的新型神經網路架構來解決佈線的問題。我們將所有的連線要求一次同時加以考慮。使用神經網路的平行架構來解 NP －完全性問題已被證明為一有效的方法，然而，將此法使用於佈線問題，本文則是首創。這套架構是由兩層的神經元所組成。第一層負責使連線的長度最小，以及分佈最平均。第二層則是負責處理通道滿溢的問題。本文亦證明此網路可以收斂至一個穩定的狀態。我們使用一組隨機產生的資料來加以測試的結果，本網路可以將連線的長度減少 20 ％左右。Item 具有可移動端點的三層VLSI通道佈線(國立台灣師範大學, 1991-06-01) 張國恩; Chang, Kuo-En本文提出在VLSI晶片上的通道佈線問題，此問題是假定通道上的端點是可被移動的。其中有兩個子問題被考慮，即是最大調齊問題與軌道指定問題。所謂最大調齊問題是重新指定各端點在通道上的位置使得能直拉的佈線能儘量多。而軌道指定問題是將所有的網列連線實際地連接在通道中。本文分別針對此兩子問題各提出啟發式的演算法解之。並以著名的實例測出這些演算法的效益。實驗結果知具有移動端點的通道佈線能夠很可觀地減少通道寬度與穿孔數。Item 學生輔導資料電腦化系統專題研究(I)(1991-07-01) 張國恩Item Layer Assignment for Multi-layer PCB and VLSI Routing(中國工程師學會, 1991-07-01) 張國恩; 方松川VLSI佈線中的佈局層指定問題是決定佈局中各線段所應處的佈局層，使得所產生的穿孔數最少。本文中，首先將多層佈局層指定問題轉換成圖形的縮減問題，然後按照所建的圖形縮減模式設計出一種啟發式的演算法以解決此問題。本演算法完成後使用著名的佈線例子以評估之。評估結果知大約有百分之 38.5 的穿孔被減少了。