Layer Assignment for Multi-layer PCB and VLSI Routing
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Date
1991-07-01
Authors
張國恩
方松川
Journal Title
Journal ISSN
Volume Title
Publisher
中國工程師學會
Abstract
VLSI佈線中的佈局層指定問題是決定佈局中各線段所應處的佈局層，使得所產生的穿孔數最少。本文中，首先將多層佈局層指定問題轉換成圖形的縮減問題，然後按照所建的圖形縮減模式設計出一種啟發式的演算法以解決此問題。本演算法完成後使用著名的佈線例子以評估之。評估結果知大約有百分之 38.5 的穿孔被減少了。
The layer assignment problem for VLSI routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. In this paper, we first transform the problem of layer assignment for multi-layer routing to the graph contractability problem and then a heuristic algorithm is proposed on the basis of the graph contractability model. The algorithm was evaluated using Deustch's five-layer difficult example. The result showed that the number of vias is reduced 38.5 percent.
The layer assignment problem for VLSI routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. In this paper, we first transform the problem of layer assignment for multi-layer routing to the graph contractability problem and then a heuristic algorithm is proposed on the basis of the graph contractability model. The algorithm was evaluated using Deustch's five-layer difficult example. The result showed that the number of vias is reduced 38.5 percent.