Please use this identifier to cite or link to this item:
|Title:||A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process|
|Publisher:||IEEE Microwave Theory and Techniques Society|
|Abstract:||A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm2, which is the smallest one compared to all reported paper.|
|Appears in Collections:||教師著作|
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.