A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process
| dc.contributor | 國立臺灣師範大學應用電子科技學系 | zh_tw |
| dc.contributor.author | Yung-Nien Jen | en_US |
| dc.contributor.author | Jeng-Han Tsai | en_US |
| dc.contributor.author | Chung-Te Peng | en_US |
| dc.contributor.author | Tian-Wei Huang | en_US |
| dc.date.accessioned | 2014-10-30T09:28:44Z | |
| dc.date.available | 2014-10-30T09:28:44Z | |
| dc.date.issued | 2009-01-01 | zh_TW |
| dc.description.abstract | A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm2, which is the smallest one compared to all reported paper. | en_US |
| dc.description.uri | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4729652 | zh_TW |
| dc.identifier | ntnulib_tp_E0611_01_013 | zh_TW |
| dc.identifier.issn | 1531-1309� | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32249 | |
| dc.language | en | zh_TW |
| dc.publisher | IEEE Microwave Theory and Techniques Society | en_US |
| dc.relation | IEEE Microwave and Wireless Components Letters, 19(1), 42-44. | en_US |
| dc.subject.other | CMOS | en_US |
| dc.subject.other | fully integrated | en_US |
| dc.subject.other | power amplifier (PA) | en_US |
| dc.subject.other | 24 GHz. | en_US |
| dc.title | A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process | en_US |