A 60-GHz CMOS power amplifier with built-in pre-distortion linearizer

Jeng-Han Tsai; Chung-Han Wu; Hong-Yuan Yang; Tian-Wei Huang

A 60-GHz CMOS power amplifier with built-in pre-distortion linearizer

Date

2011-12-01

Authors

Jeng-Han Tsai

Chung-Han Wu

Hong-Yuan Yang

Tian-Wei Huang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Abstract

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power ampli- ﬁer (PA) achieves a of 10.72 dBm and of 7.3 dBm from 1.2 V supply. After linearization, the has been doubled from 7.3 to 10.2 dBm and the operating PAE at consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.