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Title: A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications
Authors: 國立臺灣師範大學電機工程學系
Chien-Hung Kuo
Kuan-Yi Lee
Shuo-Chau Chen
Issue Date: 3-Dec-2008
Abstract: In this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage.
Other Identifiers: ntnulib_tp_E0610_02_009
Appears in Collections:教師著作

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