A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications

dc.contributor 國立臺灣師範大學電機工程學系 zh_tw
dc.contributor.author Chien-Hung Kuo en_US
dc.contributor.author Kuan-Yi Lee en_US
dc.contributor.author Shuo-Chau Chen en_US
dc.date.accessioned 2014-10-30T09:28:41Z
dc.date.available 2014-10-30T09:28:41Z
dc.date.issued 2008-12-03 zh_TW
dc.description.abstract In this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage. en_US
dc.description.uri http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4746247 zh_TW
dc.identifier ntnulib_tp_E0610_02_009 zh_TW
dc.identifier.uri http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32218
dc.language en zh_TW
dc.relation IEEE Asia Pacific Conference on Circuits and Systems APCCAS08, Macao, pp. 1224-1227. en_US
dc.title A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications en_US