透過混合式 NTT/FFT 分段設計提升 Kyber 演算法之 Side-Channel Attack 抵抗能力
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2025
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量子計算技術的快速發展使傳統公鑰加密演算法面臨潛在破解風險,後量子密碼學(Post-Quantum Cryptography, PQC)因而成為資訊安全的重要發展方向。Kyber 作為基於網格問題的代表性 PQC 演算法,雖具備強大的抗量子攻擊能力,但在硬體實作層面仍存在旁通道攻擊(Side-Channel Attack, SCA)的風險。特別是解密流程中的多項式乘法,因其執行時間高度穩定,易被攻擊者藉由時序分析推測密鑰資訊。為降低此風險,本研究提出一種結合數論變換(NTT)與快速傅立葉變換(FFT)的混合式分段運算架構,應用於 Kyber 的解密流程。該架構將多項式拆分為多段子多項式,並在每段運算中隨機選擇使用 NTT 或 FFT,使解密執行時間呈現不規律性,以干擾攻擊者的時間分析。研究以 Chipyard 開源硬體平台為基礎,整合 RISC-V 處理器與 FFT 硬體加速器,並於 Genesys2 FPGA 上進行實作與驗證。實驗結果顯示,所提出的混合式架構在不影響解密正確性的前提下,能有效增加執行時間的隨機性,並保持在可接受的硬體資源消耗範圍內。此結果證實該設計具備實作可行性及抗時間型 SCA 的潛力,為未來後量子密碼學的安全部署提供實用參考。
The rapid advancement of quantum computing poses potential threats to traditional public-key cryptographic algorithms, making Post-Quantum Cryptography (PQC) an essential focus in information security. Kyber, a lattice-based PQC scheme, provides strong resistance against quantum attacks; however, its hardware implementations remain vulnerable to Side-Channel Attacks (SCA). In particular, the polynomial multiplication in the decryption phase exhibits highly consistent execution time, allowing attackers to infer private key information through timing analysis.To mitigate this risk, this study proposes a segmented hybrid computation architecture that combines Number Theoretic Transform (NTT) and Fast Fourier Transform (FFT) in the Kyber decryption process. The proposed method divides polynomial multiplication into multiple segments, with each segment randomly selecting either NTT or FFT, introducing execution-time irregularities to interfere with timing-based SCA. The design is implemented on the open-source Chipyard hardware platform, integrating a RISC-V processor with an FFT hardware accelerator, and validated on the Genesys2 FPGA. Experimental results demonstrate that the proposed hybrid architecture effectively increases execution-time randomness without compromising decryption correctness while maintaining acceptable hardware resource usage. These results confirm the feasibility and SCA-resistance potential of the proposed method, providing practical insights for secure deployment of post-quantum cryptographic schemes.
The rapid advancement of quantum computing poses potential threats to traditional public-key cryptographic algorithms, making Post-Quantum Cryptography (PQC) an essential focus in information security. Kyber, a lattice-based PQC scheme, provides strong resistance against quantum attacks; however, its hardware implementations remain vulnerable to Side-Channel Attacks (SCA). In particular, the polynomial multiplication in the decryption phase exhibits highly consistent execution time, allowing attackers to infer private key information through timing analysis.To mitigate this risk, this study proposes a segmented hybrid computation architecture that combines Number Theoretic Transform (NTT) and Fast Fourier Transform (FFT) in the Kyber decryption process. The proposed method divides polynomial multiplication into multiple segments, with each segment randomly selecting either NTT or FFT, introducing execution-time irregularities to interfere with timing-based SCA. The design is implemented on the open-source Chipyard hardware platform, integrating a RISC-V processor with an FFT hardware accelerator, and validated on the Genesys2 FPGA. Experimental results demonstrate that the proposed hybrid architecture effectively increases execution-time randomness without compromising decryption correctness while maintaining acceptable hardware resource usage. These results confirm the feasibility and SCA-resistance potential of the proposed method, providing practical insights for secure deployment of post-quantum cryptographic schemes.
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後量子密碼學, Kyber, 旁通道攻擊, NTT, FFT, RISC-V, Chipyard, Post-Quantum Cryptography, Kyber, Side-Channel Attack, NTT, FFT, RISC-V, Chipyard