二階前饋式誤差回授架構之雜訊移頻逐次逼近暫存式類比數位轉換器
No Thumbnail Available
Date
2025
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
隨著物聯網(Internet of Things , IoT) 技術的快速發展，越來越多的應用對高解析度和低功率消耗的類比數位轉換器提出了更高的需求，都需要在節能的情況下提供穩定且精確的數據轉換。因此先進的類比數位轉換器技術在支持這些應用中扮演著關鍵角色，特別是具備超過250kHz頻寬的類比數位轉換器，可以適應多數物聯網設備的數據傳輸需求，實現高效的數據處理。使用雜訊移頻逐次逼近暫存器 (NS-SAR) 相對傳統快閃式(Flash)暫存器可大幅減少功率消耗，以實現低功率消耗高解析度類比數位轉換器為本論文目標。提出了一個使用二階積分器前饋 (Cascaded Integrators with Distributed Feedforward, CIFF)雜訊移頻逐次逼近暫存器 (NS-SAR) 類比數位轉換器，結合了誤差回授(Error-Feedback)結構技術。設計中使用了一階主動電路，透過操作轉導放大器搭配一階被動電路，由單位增益緩衝器輔助，以開關切換模式實現了鋒利的雜訊轉移函數。透過電容之間的電荷累積，並將九位元量化器產生的量化誤差進行回授，結合主動電路的高解析度與穩定性以及被動電路的低功率消耗特性。晶片採用台積電0.18um標準CMOS製成，在10 MHz取樣頻率下，於250kHz的頻寬內實現了78.13 dB的訊號雜訊失真比，功率消耗為232uW，工作電壓為1.5V。在250kHz和625kHz頻寬下，FoMs皆超過165 dB。在625kHz頻寬下的FoMw為48.5 [fJ/step]。
With the rapid development of Internet of Things (IoT) technology, an increasing number of applications demand high-resolution and low-power ADCs that can provide stable and accurate data conversion under energy-saving conditions. Particularly, ADCs with bandwidths exceeding 250kHz can meet the data transmission requirements of most IoT devices, enabling efficient data processing. Using NS-SAR technology can significantly reduce power consumption compared to traditional Flash ADCs. This paper aims to achieve a low-power, high-resolution ADC.A second-order CIFF NS-SAR ADC with an EF structure technique is proposed. The design incorporates a first-order active circuit using an Operational Transconductance Amplifier alongside a first-order passive circuit, assisted by a Unity-Gain Buffer in a switched-mode configuration. By accumulating charge between capacitors and feeding back the quantization error generated by a 9-bit quantizer, the design combines the high resolution and stability of the active circuit with the low power consumption of the passive circuit. The chip is fabricated using TSMC 0.18μm standard CMOS technology. At a 10 MHz sampling frequency, it achieves an SNDR of 78.13 dB over a 250kHz bandwidth with a power consumption of 232μW at a supply voltage of 1.5V. The FoMs exceed 165 dB at both 250kHz and 625kHz bandwidths, and the FoMw reaches 48.5 fJ/step at 625kHz.
With the rapid development of Internet of Things (IoT) technology, an increasing number of applications demand high-resolution and low-power ADCs that can provide stable and accurate data conversion under energy-saving conditions. Particularly, ADCs with bandwidths exceeding 250kHz can meet the data transmission requirements of most IoT devices, enabling efficient data processing. Using NS-SAR technology can significantly reduce power consumption compared to traditional Flash ADCs. This paper aims to achieve a low-power, high-resolution ADC.A second-order CIFF NS-SAR ADC with an EF structure technique is proposed. The design incorporates a first-order active circuit using an Operational Transconductance Amplifier alongside a first-order passive circuit, assisted by a Unity-Gain Buffer in a switched-mode configuration. By accumulating charge between capacitors and feeding back the quantization error generated by a 9-bit quantizer, the design combines the high resolution and stability of the active circuit with the low power consumption of the passive circuit. The chip is fabricated using TSMC 0.18μm standard CMOS technology. At a 10 MHz sampling frequency, it achieves an SNDR of 78.13 dB over a 250kHz bandwidth with a power consumption of 232μW at a supply voltage of 1.5V. The FoMs exceed 165 dB at both 250kHz and 625kHz bandwidths, and the FoMw reaches 48.5 fJ/step at 625kHz.
Description
Keywords
類比數位轉換器, 雜訊移頻逐次逼近暫存器, 誤差回授, 積分器前饋, Analog-to-Digital Converters, Noise-Shaping Successive Approximation Register, Error-Feedback, Cascaded Integrators with Distributed Feedforward