AES之超大型積體電路設計

Abstract

高等加密標準(Advanced Encryption Standard, AES)硬體實現在現場可程式邏輯閘陣列(FPGA)與特殊用途積體電路(ASIC)已經被很廣泛的討論，尤其是如何達到數十億吞吐量的議題；然而本實驗室近幾年在FPGA設計成果很多，但尚未實現標準元件設計，因此本研究將實驗室團隊開發的AES硬體架構改善，並架設工作站透過數位電路設計流程實現AES加密晶片。 首先本研究利用國家晶片研究中心提供的工具，將數位電路設計所需的環境與軟硬體架設起來，建立一套完整的數位晶片設計平台。接著本研究提出8位元輸入輸出的AES硬體電路架構，並搭配BRAM(包含RAM和ROM)，或使用組合邏輯運算去設計，分析其在電路設計上實現在FPGA與透過標準元件設計流程實現在ASIC上，從數據得知，其未使用BRAM的8位元輸入輸出的AES gate count為2.2k，是在目前搜尋文獻中面積最小的設計。

Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC have been intensely discussed, especially in high-throughput of Giga bit per second (Gbps). However, our team have many designs in FPGA in the recent years but not yet implemented in Cell-Based Design. Therefore, this paper improve the hardware architecture of AES , setup the environment and server , Then through Cell-Based Design flow to implement the AES Chip. First, this paper use the EDA tools provided by the National Chip Implementation Center to setup the environment for a complete platform of digital chip design. Then, This paper presents an 8-bit AES implementation with BRAM (using RAM or ROM) or without BRAM(using combinational circuits) in order to achieve design. Finally, we compare the data of FPGA and ASIC. By the results of ASIC, the area of AES without BRAM is 2.2k gate count, which is the smallest design among literature reports.