基於硬體資源優化的廣義迴歸神經網路FPGA設計-以QoS應用為例
| dc.contributor | 黃文吉 | zh_TW |
| dc.contributor | Hwang, Wen-Jyi | en_US |
| dc.contributor.author | 林宇恩 | zh_TW |
| dc.contributor.author | Lin, Yu-En | en_US |
| dc.date.accessioned | 2025-12-09T08:19:20Z | |
| dc.date.available | 2030-08-06 | |
| dc.date.issued | 2025 | |
| dc.description.sponsorship | 資訊工程學系 | zh_TW |
| dc.identifier | 61247083S-48161 | |
| dc.identifier.uri | https://etds.lib.ntnu.edu.tw/thesis/detail/4a9f2446f9275e94d75b0daf19409a7c/ | |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/125839 | |
| dc.language | 中文 | |
| dc.title | 基於硬體資源優化的廣義迴歸神經網路FPGA設計-以QoS應用為例 | zh_TW |
| dc.title | FPGA-Based Area-Optimized Design of General Regression Neural Network for QoS Applications | en_US |
| dc.type | 學術論文 |