基於三角積分調變器之D類功率放大器

dc.contributor郭建宏zh_TW
dc.contributorKuo, Chien-Hungen_US
dc.contributor.author林聖淇zh_TW
dc.contributor.authorLin, Sheng-Chien_US
dc.date.accessioned2019-09-03T10:45:46Z
dc.date.available不公開
dc.date.available2019-09-03T10:45:46Z
dc.date.issued2017
dc.description.abstract隨著時間的進行,人們對生活品質的要求總是好還要更好,尤其是幾乎每個人每天都會隨身帶著的智慧型行動裝置更是日新月異,近年來發展的攜帶型行動裝置內部皆有一個功率放大器用以驅動內建的喇叭(Lout Speaker),而D類放大器能減少熱能的產生,且不需要散熱裝置,因此相較於A類與AB類功率放大器來說有著較好的轉換效率與較小的體積,符合了目前攜帶型行動裝置需要低耗電與小體積的趨勢。 本論文之D類放大器採用一個新的架構,藉由2階3位元三角積分調變器之9位階數位輸出訊號產生控制D類功率放大級之控制訊號,運用較為簡單的控制方法,讓多位元的三角積分調變器也能順利控制D類功率放大器之功率放大級運作。最後則藉由回授來增加整體線性度。 本論文使用TSMC 0.18 μm 1P6M 標準CMOS製程,供應電壓為1.8V與3V,系統頻寬為25 kHz,取樣頻率為2.56MHz,OSR為51.2,輸入訊號頻率為7.1875kHz,輸入訊號振幅為-13.86 dB,所得到之訊號雜訊比為78.5dB,THD為0.0095%,總消耗功率為145mW。zh_TW
dc.description.abstractA new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 9-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78.5 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.0095% at a power consumption of 145 mW.en_US
dc.description.sponsorship電機工程學系zh_TW
dc.identifierG060375032H
dc.identifier.urihttp://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22G060375032H%22.&%22.id.&
dc.identifier.urihttp://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/95660
dc.language中文
dc.subjectD類功率放大器zh_TW
dc.subject開關放大器zh_TW
dc.subject三角積分調變D類功率放大器zh_TW
dc.subjectClass-D Amplifieren_US
dc.subjectSwitching Amplifieren_US
dc.subjectDelta- Sigma Class-D Amplifieren_US
dc.title基於三角積分調變器之D類功率放大器zh_TW
dc.titleA Delta-Sigma Modulator-Based Class-D Amplifieren_US

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