X頻帶CMOS功率放大器設計

Abstract

X 頻帶有許多重要的應用，如軍事、雷達、衛星通訊及科學研究等。在過去，砷化鎵(GaAs)擬晶性高電子遷移率電晶體(Pseudomorphic High Electron MobilityTransistor, pHEMT)擁有高崩潰電壓、低雜訊等優點因此成為X 頻帶的主流。近年來，由於製程的改進，使CMOS 製程適合應用於X 頻帶，然而由於CMOS 製程中低崩潰電壓元件與高損耗的矽基板，在X 頻帶中高功率表現的CMOS 功率放大器設計仍是個挑戰。本論文基於 0.18 μm CMOS 製程，提出兩個應用於CMOS X 頻帶的功率放大器。第一個晶片採用兩路直接並聯電晶體與功率結合變壓器，透過最佳化變壓器之尺寸與輸入匹配電容，可達到雙倍輸出功率與較小的晶片面積。經由量測結果，第一顆功率放大器在10 GHz 飽和功率(Psat)輸出為23.1 dBm，功率附加效率(PAE)為12%。此晶片在8.6 GHz 有最佳表現，飽和功率(Psat)輸出為24.8 dBm，功率附加效率(PAE)為20%。含pad 之晶片面積為0.78 mm2。為了進一步提升輸出功率，第二顆晶片採用平行結合變壓器(PCT)技術，結合三組差動式功率放大器。由於較小的元件的尺寸，阻抗轉換比降低，因此簡化了輸出匹配網路設計。經由量測結果，第二顆功率放大器在10 GHz 達到了高的飽和功率(Psat)26 dBm，功率附加效率(PAE)為12.5%。此晶片在9GHz 有最佳表現，飽和功率(Psat)輸出為27.1 dBm，功率附加效率(PAE)為22%。含pad 之晶片面積只有0.88 mm2。There are many important applications in X band, such as military, radar, satellite communication, and scientific research. In the past, GaAs pseudomorphic high electron mobility transistor (pHEMT) provides high mobility of electrons and high quality factor of the passive components dominate this field. Recently, CMOS process is suitable for X-band due to the improvement of CMOS process. However, because of the low breakdown voltage and lossy silicon substrate of the CMOS process, design of CMOS power amplifier (PA) with high power performance is still a challenge for the X-band. In this thesis, two CMOS power amplifiers were designed and fabricated in TSMC1P6M 0.18 μm CMOS process for X-band applications. The first power amplifier IC utilizes two-way direct shunt power combining and transformer power combining technique. Through the optimized transformer size and input matching capacitor, doubled output power and compact chip size can be achieved. The output power of the first PA is 23.1 dBm and power added efficiency (PAE) is 12% at 10 GHz from measurement. The best output power performances is 24.8 dBm with peak power added efficiency (PAE) of 22% at 8.6 GHz. The chip area including pad is 0.78mm2.To further enlarge the output power, the second power amplifier employs Parallel Combining Transformer (PCT) technique to combine three deferential power amplifier units. The smaller transistor size in each power amplifier unit is selected, the required impedance transformation is reduced, and the output matching network can be simplified. The second PA achieves high output power of 26.8 dBm at 10 GHz with peak power added efficiency (PAE) of 12.5% at 10 GHz from measurement. The best output power performances is 27.1 dBm with peak power added efficiency (PAE) of22% at 9 GHz. The chip area including pad is only 0.88mm2 .