貴金屬/氧化鋅薄膜結構的電阻轉換

Abstract

本研究系統性分析以ZnO為主動層之電阻式隨機存取記憶體(RRAM)元件，探討其在常溫、400℃、常溫鍍膜並快速熱退火等三種製備方式、50~120 nm的ZnO厚度與Au/Au、Pt/Au、Pt/Pt等三種電極結構下之電阻轉換特性。實驗結果顯示，這些元件的電流電壓特性呈線性，平均總電阻在2~320 Ω之間，平均電阻轉換率在0.1~21%之間。此轉換率代表在這些元件具有極低的電阻轉換特性，主要是因為其良好的導電性，而缺乏可由電場控制的導電絲。在製程條件方面，常溫鍍膜樣品由於晶體結構較差，可能產生較多缺陷，有助於導電通道的形成與重設，整體轉換率較高；相對地，400 °C中溫鍍膜樣品與常溫鍍膜後經快速熱退火處理之樣品，因晶體結構較完整、缺陷濃度較低，導致其電阻轉換率較低。在電極結構方面，Pt/ZnO/Au元件整體轉換率提升，推測與Pt為高功函數材料，可提升界面勢壘並強化局部電場，進而促進場控導電絲的形成有關。Pt/ZnO/Pt元件的整體轉換率最好，即使在120 nm厚度條件下仍能維持穩定且較高的轉換率(約10~15%)，表現優於Pt/ZnO/Au元件。此結果顯示，對稱高功函數界面可能具備較佳的厚度適應性與導電通道控制能力。綜合分析指出，ZnO厚度在120 nm可獲得最佳的轉換率，而採用常溫製程與Pt/Pt電極配置，可進一步優化缺陷分佈與導通通道形貌，對元件轉換行為具顯著改善效果。未來可透過缺陷工程(如摻雜或沉積氣氛調控)改善氧空缺的濃度與分佈，以進一步提升ZnO型RRAM元件在非揮發性記憶體應用中的穩定性與可控性。

This study systematically investigated the resistive switching characteristics of resistive random access memory (RRAM) devices using ZnO as the active layer. The analysis covered three fabrication approaches—room-temperature (RT) deposition, 400 °C deposition, and RT deposition followed by rapid thermal annealing (RTA)—with ZnO thicknesses ranging from 50 to 120 nm, and three electrode configurations: Au/Au, Pt/Au, and Pt/Pt.Experimental results show that all devices exhibit linear current–voltage (I–V) behavior, with average total resistance ranging from 2 to 320 Ω and average resistance switching ratios between 0.1% and 21%. These low switching ratios suggest that the devices exhibit very weak resistive switching behavior, primarily due to their high conductivity and the lack of electric-field-controllable conductive filaments.In terms of processing conditions, RT-deposited samples, which likely contain more defects due to inferior crystallinity, demonstrate higher switching ratios. These defects may facilitate the formation and rupture of conductive paths. In contrast, devices fabricated at 400 °C or subjected to RTA exhibit lower switching ratios, likely due to their improved crystallinity and lower defect densities.Regarding electrode structures, Pt/ZnO/Au devices show enhanced switching ratios, which may be attributed to the high work function of Pt that increases interfacial barrier height and strengthens the local electric field, thereby promoting field-controlled filament formation. Among all configurations, Pt/ZnO/Pt devices exhibit the best overall switching performance. Even at a ZnO thickness of 120 nm, they maintain a stable and relatively high switching ratio (10~15%), outperforming Pt/ZnO/Au structures. These findings suggest that symmetric high–work-function interfaces may offer better thickness tolerance and improved control over conductive path formation.In summary, a ZnO thickness of 120 nm provides the optimal switching ratio. Devices fabricated via RT deposition and employing a Pt/Pt electrode structure further optimize defect distribution and filament morphology, significantly improving switching behavior. Future work may focus on defect engineering—such as doping or controlling the deposition ambient—to regulate the concentration and distribution of oxygen vacancies, thereby enhancing the stability and controllability of ZnO-based RRAM devices for non-volatile memory applications.