新世代電晶體及記憶體控制單元
Abstract
現今CMOS工業正朝著「微小化」的趨勢向前邁進，而為了突破
摩爾定律的物理極限，於是在本實驗中先改善應用在記憶體上控制元
件的結構與製程條件，接著再改善穿隧場效電晶體以達到摩爾定律。
本實驗在一開始先利用模擬來尋求n/p/n bi-direction diode 最佳
化的結構與製程條件，然後製作出元件並使之廣泛的應用於記憶體結
構上，接下來將發展異質接面電晶體(BJT)如 金屬/介電質/金屬或金
屬/半導體/金屬的結構，與記憶體控制元件結合；接著經由實驗証實
高介電值/金屬閘極置於最後一步製程並應用在p 型的穿隧場效電晶
體，並發現在不同結晶方向的基板上對圓型元件的影響。最後討論p
型的穿隧場效電晶體在同樣高介電值/金屬閘極與同結晶方向(110)機
板上，高濃度鍺參雜與純矽的不同，並且在結晶方向(110)上不同電流
方向所造成的影響。
In order to follow Moore’s law and beyond the physical limitation, the trend of CMOS industry is developing toward scaling down. Therefore, the technology of stackable memory devices and advanced FET had been studied in this work. In order to optimize the bi-direction devices, we used TCAD simulator for the process and structure design, as well as the M/I/M and M/S/M prepared. The HKMG p-TFET had been demonstrated for advanced FET with the gate last process. We also discuss the mechanism of the substrate orientation and anisotropic effect on ON-current of SiGe (110). The G-FET has been design and prepare for high performance FET with Tunneling mechanism.
In order to follow Moore’s law and beyond the physical limitation, the trend of CMOS industry is developing toward scaling down. Therefore, the technology of stackable memory devices and advanced FET had been studied in this work. In order to optimize the bi-direction devices, we used TCAD simulator for the process and structure design, as well as the M/I/M and M/S/M prepared. The HKMG p-TFET had been demonstrated for advanced FET with the gate last process. We also discuss the mechanism of the substrate orientation and anisotropic effect on ON-current of SiGe (110). The G-FET has been design and prepare for high performance FET with Tunneling mechanism.
Description
Keywords
新世代電晶體及記憶體控制單元