矽奈米線場效電晶體之研究
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2008
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當半導體元件微縮至深次微米之領域時，金氧半場效電晶體具環繞閘極結構能有效降低短通道效應且具備理想之次臨界斜率。短通道效應使得元件應用數位電路時，產生漏電流導致不必要之功率消耗，進而影響電路的功能。因此研究矽奈米線場效電晶體元件元件成為刻不容緩之事。
本論文研究利用已經發展成熟的矽半導體製程技術，與熱氧化應力限制原理，設計製作完全環繞式閘極之矽奈米線場效電晶體元件。本研究之矽奈米線場效電晶體，其奈米線定義範圍為直徑20～50奈米、長度200～400奈米。於室溫下量測其元件特性，發現其電性除完美呈現出標準場效電晶體之特性外，於某些元件中更呈現出庫倫阻斷現象之特性。我們推測形成電流-電壓特性圖呈現階梯現象之原因，乃為絕緣層上之矽元件層進行摻雜製程時，恰巧於通道中形成砷島所造成。本研究結果成功利用熱氧化應力限制原理製作出直徑50奈米以下之矽奈米線。
As semiconductor devices are scaled into to the deep submicron meter regime, surrounding-gated silicon on insulator metal-oxide-semiconductor field effect transistors have shown promise in both the short-channel effect and in achieving a nearly ideal subthreshold slope. To control the surrounding-gated SOI MOSFET’s very well, when they are applied to the VLSI, there is a need to develop an accurate model for the suspended silicon nanowire field effect transistors. In this study, we use the well developed silicon semiconductor process and the Stress Limited Oxidation to fabricate fully-surround gated silicon nanowire field effect transistor. The present SiNW-FET had dimensions of 20 ~ 50 nm in diameter and 200 ~ 400 nm in length, and exhibited well pronounced classical field effect transistor characteristics and Coulomb-blockade phenomena at room temperature. The I=V staircases may be attributed to charging of As islands with sizes in the nanometer region, formed by As atoms from the top silicon layer of SOI wafer during ion implantation. These results open a new path to build a SiNWs by minimizing the diameter below 50 nm.
As semiconductor devices are scaled into to the deep submicron meter regime, surrounding-gated silicon on insulator metal-oxide-semiconductor field effect transistors have shown promise in both the short-channel effect and in achieving a nearly ideal subthreshold slope. To control the surrounding-gated SOI MOSFET’s very well, when they are applied to the VLSI, there is a need to develop an accurate model for the suspended silicon nanowire field effect transistors. In this study, we use the well developed silicon semiconductor process and the Stress Limited Oxidation to fabricate fully-surround gated silicon nanowire field effect transistor. The present SiNW-FET had dimensions of 20 ~ 50 nm in diameter and 200 ~ 400 nm in length, and exhibited well pronounced classical field effect transistor characteristics and Coulomb-blockade phenomena at room temperature. The I=V staircases may be attributed to charging of As islands with sizes in the nanometer region, formed by As atoms from the top silicon layer of SOI wafer during ion implantation. These results open a new path to build a SiNWs by minimizing the diameter below 50 nm.
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Keywords
矽奈米線, 場效電晶體, Silicon Nanowire, Field Effect Transistor