鐵電場效電晶體寫入後讀取速度及鐵電隨機存取記憶體印記效應研究

Abstract

隨著非揮發性記憶體（Non-Volatile Memory, NVM）技術廣泛應用於人工智慧（Artificial intelligence, AI）與嵌入式系統領域，鐵電隨機存取記憶體（Ferroelectric Random Access Memory, FeRAM）與鐵電場效電晶體（Ferroelectric Field-Effect Transistor, FeFET）因具備高速、低功耗與互補式金屬氧化物半導體（Complementary Metal-Oxide-Semiconductor, CMOS）相容等優勢，被認為次世代記憶體架構的關鍵候選。然而在實際操作條件下，元件易受電子陷阱（Trap）與缺陷（Defect）影響，導致臨界電壓（Threshold Voltage, VT）漂移、記憶視窗（Memory Window, MW）衰退與資料保持性劣化等可靠度挑戰。本研究針對鐵電隨機存取記憶體與鐵電場效電晶體分別使用的元件結構為金屬-鐵電-金屬（Metal-Ferroelectric-Metal, MFM）與環繞式閘極（Gate-All-Around, GAA），探討元件在電子陷阱分佈與內建電場形成交互作用下的電性行為。於鐵電場效電晶體部分，提出雙層鐵電氧化鉿鋯（HfZrO2, HZO）夾氮化鈦（Titanium Nitride, TiN）結構，透過上下層厚度差異設計矯頑場（Coercive Field）不對稱性，並抑制短延遲讀取下的電子陷阱行為，有效提升高速讀寫下之寫入後讀取（Read-After-Write）穩定性。於鐵電隨機存取記憶體部分，則藉由控制溫度與厚度變因，系統性分析印記效應（Imprint Effect），並證實其由極化導致的陷阱再分佈與氧空缺（Oxygen Vacancies, VO）狀態變化所主導。實驗結果顯示，陷阱行為與內建電場交互作用為鐵電記憶體失效之關鍵，亦為未來可靠度設計之核心議題。本研究提出結構設計與量測方法兩面向之改善策略，期望能作為高穩定度鐵電記憶體元件開發之參考。With the increasing demand for non-volatile memory (NVM) inartificial intelligence (AI) and embedded systems, ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistor (FeFET) had been identified as promising candidates due to their high speed, low power consumption, and CMOS compatibility. However, device reliability had remained a critical concern, as electron trap behavior and defect were known to induce threshold voltage shifts, memory window degradation, and data retention loss under practical operating conditions. In this study, the effect of trap distributions and internal field formation mechanisms were investigated on the electrical characteristics of FeRAM and FeFET devices, which had been using metal-ferroelectric-metal(MFM) and gate-all-around(GAA) device structures, respectively. For the FeFET, a titanium nitride (TiN) -inserted double HfZrO2 (HZO) stack had been implemented to enhance read-after-write stability under fast operation, by introducing thickness-induced asymmetric coercive fields and suppressing electron trapping under short read delay conditions. For the FeRAM, systematic thermal baking experiments had been conducted across various temperatures and film thicknesses to analyze imprint effect. The results confirmed that polarization-induced trap redistribution and oxygen vacancy transitions were the dominant mechanisms responsible of internal field-induced degradation. The findings highlighted the critical role of electron trapping and internal field coupling in the reliability of ferroelectric memory, and provided experimentally validated strategies for future device optimization in high-performance and high-density applications.