高效能逐次逼近式類比數位轉換器的設計與實現
| dc.contributor | 郭建宏 | zh_TW |
| dc.contributor | Chien-Hung Kuo | en_US |
| dc.contributor.author | 林翰江 | zh_TW |
| dc.contributor.author | Han-Chiang Lin | en_US |
| dc.date.accessioned | 2019-09-03T10:49:19Z | |
| dc.date.available | 2018-8-28 | |
| dc.date.available | 2019-09-03T10:49:19Z | |
| dc.date.issued | 2013 | |
| dc.description.abstract | 積體電路設計在製程技術的進步之下，製程技術提升可以大量降低電路佈局的面積，也使得電路運作的電壓因而縮小，使得低功率與高效能的電路設計不斷推出。可攜式的電子產品在消費市場上越來越多，輕薄短小以及電池的長時效性要求，漸漸成為電路設計之主流；尤其是應用在人體或生物上的植入性醫學晶片，為了能達到長時間使用不更換的目標，低功率在電路的設計上，更顯得重要。在眾多的類比數位轉換器中，逐次逼近式類比數位轉換器(successive approximation register analog-to-digital converter, SAR ADC)最適合應用在低功率的系統中，此架構僅需一顆比較器即可完成資料轉換，這項優點可大幅地縮減資料轉換所消耗的功耗。 在本論文中，提出兩種架構分別為，二次浮動開關電容式SAR ADC和分裂式浮動開關SAR ADC架構。在二次浮動開關電容式SAR ADC此架構中，DAC部分的功率消耗相較於傳統切換技術之DAC架構，所提出方法可有效的節省97.57%的平均能量，採用TSMC 0.18-μm 1P6M的標準製程完成，在奈式取樣頻寬的規格下，分別可達到的品質因數FOM值為105.86-fJ/conversion-step。另外，在分裂式浮動開關之SAR ADC架構，在電容佈局方面，相較於傳統DAC架構可節省96.875%的電容佈局面積，採用TSMC 0.18-μm 1P6M的標準製程完成，分別可達到的品質因數FOM值為29.47-fJ/conversion-step。 | zh_TW |
| dc.description.abstract | With the development of modern CMOS fabrication, the advancement of fabrication processing is capable of reducing the area of integrated circuit layout and lowering the voltage during circuit operation, producing a constant stream of low-power and high-performance circuits. With the raising number of portable electronic devices, portability as well as battery endurance have become the mainstream of chips performance. Especially in the application of human or biological implantation, the importance of low-power circuit design become much greater. Among different type of analog-to-digital converters (ADC), successive approximation register (SAR) is the most appropriate for low-power designs. Becouse it only takes one comparator to complete the whole sampling data during each conversion phase, which significantly reduces the power dissipation. In this thesis, there are two schemes：(1) double partial FCS scheme based single-ended SAR ADC, (2) the partial FCS scheme based differential SAR ADC .Applying double partial FCS scheme based single-ended SAR ADC can efficiently reduce 97.57% of average switching energy compared to the conventional DAC approach. Constructed by TSMC 0.18-μm 1P6M process technology, the presented SAR ADC can achieve 105.86-fJ/conversion-step figure of merit (FOM) in the Nyquist bandwidth. In addition, applying the partial FCS scheme based differential SAR ADC can efficiently reduce 96.875% of Capacitor layout area compared to the conventional DAC approach. Constructed by TSMC 0.18-μm 1P6M process technology, the presented SAR ADC can achieve 29.47-fJ/conversion-step figure of merit (FOM). | en_US |
| dc.description.sponsorship | 電機工程學系 | zh_TW |
| dc.identifier | GN0698750334 | |
| dc.identifier.uri | http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22GN0698750334%22.&%22.id.& | |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/95839 | |
| dc.language | 中文 | |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 逐次逼近暫存器 | zh_TW |
| dc.subject | 電容式數位類比轉換電路 | zh_TW |
| dc.subject | 品質因數FOM | zh_TW |
| dc.subject | Analog-to-digital converter | en_US |
| dc.subject | successive approximation register | en_US |
| dc.subject | capacitive DAC array | en_US |
| dc.subject | figure of merit (FOM) | en_US |
| dc.title | 高效能逐次逼近式類比數位轉換器的設計與實現 | zh_TW |
| dc.title | Design and Implementation of Energy Efficient Successive-Approximation Analog-to-Digital Converters | en_US |
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