低功耗與矽化物阻擋之靜電放電防護電路設計

dc.contributor蔡政翰zh_TW
dc.contributor林群祐zh_TW
dc.contributorTsai, Jeng-Hanen_US
dc.contributorLin, Chun-Yuen_US
dc.contributor.author吳士昕zh_TW
dc.contributor.authorWu, Shih-Hsinen_US
dc.date.accessioned2025-12-09T08:03:08Z
dc.date.available2027-08-01
dc.date.issued2025
dc.description.sponsorship電機工程學系zh_TW
dc.identifier61275033H-48254
dc.identifier.urihttps://etds.lib.ntnu.edu.tw/thesis/detail/8443d6af55c4e9f9fd9ffb40f664d457/
dc.identifier.urihttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/125065
dc.language英文
dc.title低功耗與矽化物阻擋之靜電放電防護電路設計zh_TW
dc.titleDesign of Low-Power and Silicide-Blocking ESD Protection Circuitsen_US
dc.type學術論文

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