視覺型同時定位與建圖系統之硬體實現
Abstract
本論文針對機器人視覺型同時定位與建圖(Visual Simultaneous Localization and Mapping, V-SLAM)計算效率之問題，將V-SLAM系統透過FPGA硬體加速電路之設計，實現一低成本、低功耗與高效能的系統，讓機器人在未知環境中能夠即時的建立三維環境地圖，同時對機器人自身位置進行定位。本論文主要是將先前學長所提出的V-SLAM系統實現於FPGA上，以硬體加速電路的優勢，利用管線化設計與平行化計算等，使V-SLAM能夠即時的提供機器人的狀態以及環境地圖。為了驗證各功能模組於硬體化電路的計算速度以及精確度，本論文採用不同的實驗平台，包括個人電腦、FPGA與Nios II等，以真實環境下所拍攝的影像資訊，依照各模組的功能分別以不同角度進行測試。實驗結果顯示，相較於一般個人電腦或Nios II，FPGA硬體加速電路功能模組於特徵比對的運算效率分別提升了約390倍與16,000倍；而在精準度的測試中，2D-to-3D特徵轉換模組與重心計算模組在FPGA的運算中，相較於軟體計算結果誤差小於1%，地圖管理模組的測試則是以雙眼攝影機的參數決定近似門檻值後，以OR邏輯閘對高位元進行判斷即可得到與軟體相同之結果。從實驗結果可知，以本論文所提出之FPGA設計方法完成之V-SLAM系統可以實現即時的機器人同時定位與建圖，具備低成本與低功耗的優勢。
This thesis addresses the problem of computational efficiency in visual simultaneous localization and mapping (V-SLAM). By implementing FPGA-based hardware acceleration to the V-SLAM system, a system design of low-cost, low power consumption, and high computational efficiency is established. This design in turn allows a robot to perform three-dimensional mapping and self-localization in an unknown environment. Building on a previous V-SLAM system, the proposed design further boosts computational efficiency and accuracy with the implementation of FPGA, taking advantage of its pipeline design and parallel computation. To validate the performances through hardware enhancement, several experimental platforms were adopted, including a typical personal computer, the proposed system with FPGA-based acceleration, and a Nios II processor. Images acquired from real environments were processed and compared in different aspects. Experimental results show that the FPGA-based system is approximately 390 and 16,000 times faster in feature matching compared to a typical PC and Nios II processor, respectively. As for accuracy comparison, the relative computational error between software and hardware of the FPGA-based system is less than 1% in terms of 2D-to-3D transformation and center of gravity estimation. The results lead to the conclusion that it is technically feasible to develop a FPGA-accelerated V-LAM system with low-cost, low power consumption, and high computational efficiency.
This thesis addresses the problem of computational efficiency in visual simultaneous localization and mapping (V-SLAM). By implementing FPGA-based hardware acceleration to the V-SLAM system, a system design of low-cost, low power consumption, and high computational efficiency is established. This design in turn allows a robot to perform three-dimensional mapping and self-localization in an unknown environment. Building on a previous V-SLAM system, the proposed design further boosts computational efficiency and accuracy with the implementation of FPGA, taking advantage of its pipeline design and parallel computation. To validate the performances through hardware enhancement, several experimental platforms were adopted, including a typical personal computer, the proposed system with FPGA-based acceleration, and a Nios II processor. Images acquired from real environments were processed and compared in different aspects. Experimental results show that the FPGA-based system is approximately 390 and 16,000 times faster in feature matching compared to a typical PC and Nios II processor, respectively. As for accuracy comparison, the relative computational error between software and hardware of the FPGA-based system is less than 1% in terms of 2D-to-3D transformation and center of gravity estimation. The results lead to the conclusion that it is technically feasible to develop a FPGA-accelerated V-LAM system with low-cost, low power consumption, and high computational efficiency.
Description
Keywords
視覺型同時定位與建圖, FPGA, 管線化設計, 平行化計算, visual simultaneous localization and mapping, FPGA, pipeline design, parallel computing