使用0.18-μm互補式金氧半製程之鎖相迴路與頻率合成器之設計與實現
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2014
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對於各類通訊系統而言，隨著操作頻率越來越高，鎖相迴路也在其扮演著越來越重要的角色，而為了適應不同通訊系統規格的應用，鎖相迴路所要求的電路規格也有所不同，但還是會以低功耗與低相位雜訊為主要目標，只是這些目標還有許多問題需要克服，因此如何在各種電路特性上做取捨是最重要的議題。
在第四章實現了應用於5 GHz的鎖相迴路，其使用變壓器回授的壓控振盪器與高速的TSPC除頻器，讓鎖相迴路能達成低功耗與降低相位雜訊的目標。此外我們在振盪器中增置一組變容器來提高電路的調變範圍，而量測的相位雜訊在正常偏壓下，載波偏移100 kHz處為-88.15 dBc/Hz；在載波偏移10 MHz處為-117.89 dBc/Hz，整體功率消耗為26.5 mW，若在低偏壓下，載波偏移100 kHz處為-90.88 dBc/Hz；在載波偏移10 MHz處為-115.8 dBc/Hz，整體功率消耗為12.12 mW，操作範圍為4.33~5.1 GHz。
第五章實現了應用於X頻段的頻率合成器，其使用交叉耦合對的LC振盪器架構、電流模式邏輯除頻器與多模除頻器，來達成降低相位雜訊的目標。並且我們在LC振盪器中增置一組電容來提高共振腔中的品質因素，以提高電路相位雜訊的表現，此外在預除電路的部分的，我們將電流模式邏輯除頻器的尾電流源部分刪除以增加其操作速度。量測的相位雜訊在正常偏壓下，載波偏移100 kHz處為-67.28 dBc/Hz；載波偏移10 MHz處為-119.3 dBc/Hz，整體功率消耗30.26 mW，若在低偏壓下，載波偏移100 kHz處為-67.28 dBc/Hz；載波偏移10 MHz處為-119.3 dBc/Hz，整體功率消耗17.01 mW，操作範圍為10.43~10.77 GHz。
When the operating frequency becomes higher, high-speed frequency phase-locked loop plays more and more important roles in any type of communication systems. To satisfy various communication system standards, the circuit specifications are also dissimilar. In addition, the low power consumption and low phase noise are still the main goals. To overcome above issue, a good tradeoff between circuit architectures and performances has to be made. In chapter four, a 5 GHz phase-locked loop has been designed and implemented. Utilizing the transformer feed-back VCO (voltage-controlled oscillator, VCO) and high-speed TSPC (true single phase clock, TSPC) divider, the PLL achieves low power consumption and low phase noise. To improve the circuit tuning range, we add a supernumerary varactor in VCO structure. When output frequency in 5 GHz, the measured phase noise are -88.15 dBc/Hz and -117.89 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 26.5 mW. The measured phase noise for low power consumption mode are -90.88 dBc/Hz and -115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 12.12 mW. The operating frequency range is from 4.33 to 5.1 GHz. In chapter five, a X-band frequency synthesizer has been developed. The cross-coupled pair LC VCO, current mode logic divider, and multi-modulus divider is adopted in the synthesizer design. In addition, to improve the circuit phase noise performance, a supernumerary capacitance is added to raise the quality factor of LC tank of the VCO. To promote the operating speed of the prescaler, we remove tail-current from CML (current-mode logic, CML) divider. When output frequency at 10.6 GHz, the measured phase noise are -67.28 dBc/Hz, –82.07 dBc/Hz and -119.36 dBc/Hz at 100 kHz, 1 MHz and 10 MHz frequency offsets, respectively. Total power consumption is 30.26 mW. The measured phase noise for low power consumption mode are -70.83 dBc/Hz and -121.71 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 17.01 mW. The circuit operating frequency range is from 10.43 to 10.77 GHz.
When the operating frequency becomes higher, high-speed frequency phase-locked loop plays more and more important roles in any type of communication systems. To satisfy various communication system standards, the circuit specifications are also dissimilar. In addition, the low power consumption and low phase noise are still the main goals. To overcome above issue, a good tradeoff between circuit architectures and performances has to be made. In chapter four, a 5 GHz phase-locked loop has been designed and implemented. Utilizing the transformer feed-back VCO (voltage-controlled oscillator, VCO) and high-speed TSPC (true single phase clock, TSPC) divider, the PLL achieves low power consumption and low phase noise. To improve the circuit tuning range, we add a supernumerary varactor in VCO structure. When output frequency in 5 GHz, the measured phase noise are -88.15 dBc/Hz and -117.89 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 26.5 mW. The measured phase noise for low power consumption mode are -90.88 dBc/Hz and -115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 12.12 mW. The operating frequency range is from 4.33 to 5.1 GHz. In chapter five, a X-band frequency synthesizer has been developed. The cross-coupled pair LC VCO, current mode logic divider, and multi-modulus divider is adopted in the synthesizer design. In addition, to improve the circuit phase noise performance, a supernumerary capacitance is added to raise the quality factor of LC tank of the VCO. To promote the operating speed of the prescaler, we remove tail-current from CML (current-mode logic, CML) divider. When output frequency at 10.6 GHz, the measured phase noise are -67.28 dBc/Hz, –82.07 dBc/Hz and -119.36 dBc/Hz at 100 kHz, 1 MHz and 10 MHz frequency offsets, respectively. Total power consumption is 30.26 mW. The measured phase noise for low power consumption mode are -70.83 dBc/Hz and -121.71 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 17.01 mW. The circuit operating frequency range is from 10.43 to 10.77 GHz.
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鎖相迴路, 頻率合成器, 交叉耦合對電壓控制振盪器, 多模除頻器, CMOS, X頻段, 低功耗, Phase-locked loop, Frequency Synthesizer, Cross-coupled pair VCO, Multi-Modulus Divider, CMOS, X-band, low power