垂直型態穿隧場效電晶體的製程及分析

dc.contributor莊紹勳zh_TW
dc.contributor李敏鴻zh_TW
dc.contributorSteve S. Chungen_US
dc.contributorM. H. Leeen_US
dc.contributor.author莊賀凱zh_TW
dc.contributor.authorJuang, He-Kaien_US
dc.date.accessioned2019-09-04T01:27:33Z
dc.date.available不公開
dc.date.available2019-09-04T01:27:33Z
dc.date.issued2015
dc.description.abstract應用穿隧機制的電晶體是近期頗被看好的新一代元件,與傳統的金氧半場效電晶體相比Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET),穿隧電晶體(Tunnel FET, TFET)具有以下幾個優點:(1)p-i-n的摻雜設計使得其漏電可有效被抑制,使得TFET相當適合作為低功率元件(2)發生能帶穿隧的區間大約只有10nm,這意謂TFET有著通道可被微縮到20nm以下的潛力(3)元件導通是依賴穿隧機制,因此可以超越MOSFET次臨界擺幅在60mV/dec的物理極限(4)TFET的臨界電壓VT是取決於能帶彎曲到出現穿隧效應時的偏壓點,隨著元件尺寸縮小,其VT roll-off現象不會像MOSFET這麼嚴重;目前研究的文獻均指出,TFET發展不如預期的最大因素就在於其導通電流難以做到跟MOSFET等元件相比,因此,就更需要找到一些方式來提升TFET的電流,本論文是利用垂直方向穿隧的機制來設計元件,藉此增加整個穿隧機制所產生的電流,提升TFET的導通電流,研究結果顯示,從導通電流的兩段上升可找到垂直穿隧電流的產生,且大面積的垂直穿隧確實能幫助TFET的導通電流提高,而源極摻雜保持在1x1019~1020cm-3會是較好的選擇,同時我們也利用模擬軟體來驗證實作元件的製程問題,發現在本論文的元件製作上,閘極氧化層是影響元件電性最主要的因素。zh_TW
dc.description.abstractRecently, a transistor with tunneling mechanism called Tunnel FET was proposed as the candidate of MOSFET. Compared to MOSFET, TFET has several advantages: (1)TFET is suitable for low power device due to the higher barrier of the reversed p-i-n junction in TFET. (2)The band-to-band tunneling region is about 10nm, so that the transistor can be shrunk down to 20nm gate length. (3)The subthreshold swing of TFET has ability to surmount 60mV/dec of MOSFET’s physical limit by its distinct working principle. (4)The threshold voltage of TFET depends on bending in the small region, but not in the whole channel region, Vt roll-off is much smaller than that of MOSFET while scaling. The major challenge of TFET is the boosting of on current. In this paper, we design a device with vertical tunneling structure for investigating how to enhance the on current of TFET. The analytic results show that we can find two parts of boosting current, the second boosting current is caused by vertical tunneling, we have proved it by band gap diagram of simulation. And the best source concentration is about 1x1019~1x1020cm-3. It can be adjusted to have appropriate threshold voltage and better subthreshold swing in this region. At the same time, we investigate the issue of fabrication by simulation. It shows that the major issue affecting our performance of device is the quality of gate oxide.The bad gate oxide induces trap assist tunneling, then the current of gate will directly tunnel through the gate oxide, and that’s where the leakage current come from.en_US
dc.description.sponsorship光電科技研究所zh_TW
dc.identifierG060148024S
dc.identifier.urihttp://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22G060148024S%22.&%22.id.&
dc.identifier.urihttp://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/97955
dc.language中文
dc.subject穿隧場效電晶體zh_TW
dc.subject垂直穿隧機制zh_TW
dc.subject矽製程zh_TW
dc.subjectTunnel FETen_US
dc.subjectvertical tunneling mechanismen_US
dc.subjectsilicon-baseden_US
dc.title垂直型態穿隧場效電晶體的製程及分析zh_TW
dc.titleFabrication and Analysis of Silicon-Based Vertical-Type Tunneling Field-Effect Transistoren_US

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