符合CMOS製程之鐵電負電容電晶體及自我對準之鰭式穿隧型電晶體試製

Abstract

在次世代COMS製程結點，改善次臨界擺幅去降低元件之操作電壓及功率損耗極為重要。而在本論文之實驗使用鐵電材料HfOX/ZrOX做為電晶體之閘極介電層(CET=0.98)，應用鐵電材料之負電容效應改善先閘極製程之電晶體次臨界擺幅。 穿隧型電晶體式使用穿隧機制，改善次臨界擺幅，而穿隧型電晶體的製程S/D方面需要clear之光罩(非自對準製程)，此種光罩在製作小線寬時最大的困難點在於光罩與光罩對準，另外在元件微縮後，會使得閘極控制力下降，造成多於功率消耗，而在論文實驗中使用鳍式結構，來加強閘極控制力，S/D使用了dark光罩(自對準製程)製作鳍式穿隧型電晶體，全程使用i-line黃光製程成功驗證自對準製程應用於鳍式穿隧型電晶體。The enhancement performance of steep swing may reduce power consumption and be a candidate of next generation technology node in CMOS industry.In this work, the superior subthreshold swing is obtained by NC effect with dielectric CET=0.98nm, which the combination of HfOX/ZrOX was used. The self-aligned fin-shaped TFET without space between gate and source/drain is demonstrated successfully, and the fabrication process using all i-line photolithograph stepper without e-beam writer. The high ON current (> 10A) is obtained and indicates the benefit of self-alignment process. The proposed fin-shaped TFET process leads the opportunity of the advanced devices fabrication by 6-inch process with i-line photolithograph stepper.