鉍接觸電極旋轉角度在二硫化鉬場效電晶體的導電度相依性探討

Abstract

近年來，在二維材料層與層間堆疊角度開展一個全新自由度來調控載子傳輸特性，顯示異質結構間的堆疊角度在追求更好的載子遷移率扮演至關重要的角色。同時，在電晶體接觸工程方面也展示了在半金屬鉍（Bi）在二硫化鉬（MoS2）場效應晶體管（FETs）中實現超低接觸電阻的顯著突破。基於這些研究基礎上，我們進一步探討以鉍金屬做為接觸電極的二硫化鉬電晶體，藉由旋轉鉍電極與二硫化鉬的接觸角度，研究導電率(conductivity)隨接觸角度的差異性。透過我們的研究顯示，導電率與接觸電極的旋轉角度改變呈現連續變化，在0°時達到最高點，並隨著接觸角度增加而導電率降低，在30°處達到最低點。這種趨勢在載子遷移率(Mobility)中也有所體現，最佳接觸角度時，載子遷移率幾乎增加一倍，且此現象與3-band tight binding理論模擬結果呈現一致的結果，顯示不同接觸電極角度情況下，在材料傳輸方向會具有不同的穿透率，進而導致電子特性隨接觸電極角度有所變化。此外，我們也進一步對於不同二硫化鉬晶格方向電子傳輸特性的探討，結果顯示，不論是Zigzag(ZZ)或是Armchair(AC)方向，導電率與載子遷移率均無顯著差異，顯示在二硫化鉬中不同晶格方向間的傳輸等向性。這項研究的意義延伸至通過精確管理材料之間晶格失配來提升器件性能的潛力，有望顯著提高計算速度和工作效率，為異質集成電路提供了廣闊的前景。In recent years, the interlayer stacking angle of two-dimensional (2D) materials has been identified as a critical parameter for modulating carrier transport properties, demonstrating its importance in optimizing carrier mobility in heterostructures. Concurrently, advancements in transistor contact engineering have shown that semi-metal bismuth (Bi) can achieve ultra-low contact resistance in molybdenum disulfide (MoS2) field-effect transistors (FETs).Building on this foundation, we investigated MoS2 transistors with Bi metal contacts, examining conductivity variations with different rotational angles of the Bi electrodes relative to the MoS2. Our results indicate that conductivity peaks at 0° and decreases with increasing contact angle, reaching a minimum at 30°. This trend is also reflected in carrier mobility, which nearly doubles at the optimal angle. These findings align with 3-band tight-binding theoretical simulations, suggesting that different contact angles alter transmission probabilities within the material, affecting its electronic properties.Additionally, our exploration of electronic transport properties along different lattice directions of MoS2 revealed no significant differences in conductivity and mobility between the Zigzag (ZZ) and Armchair (AC) directions, indicating isotropic transport. This research highlights the potential for enhancing device performance through precise control of lattice mismatches, offering promising prospects for heterogeneous integrated circuits and improved power efficiency and computational speed.