38GHz 鏡像抑制混頻器與可變增益放大器設計

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隨著毫米波頻段的發展,在相位陣列(Phase Array)架構的射頻收發器系統中,混頻器與可變增益放大器為相當重要的元件。由於互補式金氧半導體製程(CMOS)具有低成本以及高整合度的優勢,所以被廣泛地運用於毫米波的電路設計上。因此本論文將使用 TSMC 65nm CMOS 製程,設計實現 38 GHz 鏡像抑制混頻器與可變增益放大器。 本論文第一顆電路為鏡像抑制降頻器,採用I/Q 訊號調變的方式消除鏡像訊號,並透過耦合器在寬頻下做到兩正交訊號振幅與相位匹配,來達到寬頻的鏡像拒斥比。此外在 IF 端加上緩衝放大器來提升整體轉換增益。當LO的驅動功率為 3 dBm時,在 34 GHz 至 43 GHz時的鏡像拒斥比皆小於- 30 dBc,轉換增益為 -6±1 dB,功耗約為9.72 mW,晶片佈局面積為780 μm × 760 μm。 第二顆電路為 38 GHz可變增益放大器,透過數位控制技術來調整可變增益範圍,採用一級的電流控制架構(Current Steering)來實現。透過在電流控制架構加上Body Bias,此架構能讓可變增益放大器在低偏壓的操作下,提供足夠的可調增益範圍。當供應電壓 Vdd 為 1.2 V時,於 38 GHz 有最高增益 14.96dB,可變增益範圍則是在 6.68 dB ~ 14.96dB,約有 8.28 dB,整體功率消耗約為 33 mW,晶片佈局面積為 400 μm × 800 μm。
Mixer and Variable Gain Amplifier (VGA) play an important role in the Phase-array radio frequency transceiver. Complementary Metal-Oxide Semiconductor (CMOS) process has been widely used for mmWave circuit design due to the advantage of low cost and high integration. In this paper, 38 GHz Image Rejection Mixer and VGA are presented and implemented in TSMC 65nm CMOS technology. First, a 38GHz Image Rejection Mixer has presented and implemented. Eliminating the image signal by adapting I/Q signal modulation, also achieving a wideband amplitude and phase match of two quadrature signals by coupler. So can acquire a wideband Image Rejection Ratio(IRR). In addition, put a buffer amplifier at IF port to improve conversion gain for the mixer.The conversion gain is -6±1 dB at LO power of 3 dBm and lower than -30 dBc Image Rejection Ratio when the mixer ranged from 34 GHz to 43 GHz. The DC power Power consumption is 9.72 mW, and the chip size is 760 μm × 780 μm. Second, a 38 GHz Variable Gain Amplifier (VGA) has designed and implemented. To achieve wide variable gain range, we utilized digital control techniques which adopted one current steering stages.Integrating Body bias into the current steering architecture, which can provide sufficient Gain Control Range for VGA with low voltage supply. When the supply voltage is 1.2 V, the VGA has a peak gain of 14.96dB at 38 GHz. The variable gain range is from 6.68 dB to 14.96dB with a range of 8.28 dB. The DC power consumption is 33 mW, and the chip size is 400 μm × 800 μm.



鏡像抑制混頻器, 鏡像拒斥比, 互補式金氧半導體, 可變增益放大器, 電流控制架構, 基極偏壓, Image Rejection Mixer, Image Rejection Ratio (IRR), Complementary Metal Oxide Semiconductor (CMOS), Variable Gain Amplifier (VGA), Current Steering, Body Bias