NEO 與 GHA 多通道棘波分類系統之低功率電路設計

Abstract

本研究旨在完成一可植入式棘波分類晶片之電路設計與合成。由於植入式晶片與大腦緊密接觸，晶片面積太大會壓迫腦部，功耗太大可能會導致腦細胞受損，不可不慎。因此在設計時，晶片的面積與功耗會成為重要考量。

本研究提出基於NEO演算法的棘波偵測器以及基於GHA演算法的特徵擷取器，配合架構上的運算單元共享，設計出高效能、低功耗、低面積的電路架構。本研究並且將電路實作於ASIC流程上，相對於FPGA開發，可更有彈性的調整晶片的面積與功耗。本研究也導入了clock gating技術，透過抑制記憶體單元的動態功耗，進一步降低晶片的耗電量。

本論文最後提出電路架構的瓶頸分析，並根據分析結果，選出數組最佳參數進行進一步的面積、功耗分析。我們證明所設計出來的晶片比起其他現有的架構，有更好的面積、功耗表現，並證明clock gating在節省功耗上起了關鍵作用。本論文也簡短討論並說明GHA作為特徵擷取演算法，與在此領域常用的PCA演算法的擷取效果相去不遠，實為一有效率之替代方案。

This research aims to design an implantable spike sorting chip. To minimize possible damage to human brain, the chip area and power consumption specification should be planned carefully.

A spike sorting circuit containing spike detection unit and feature extraction unit is developed. The spike detection unit implements the Nonlinear Energy Operator (NEO) algorithm, and the feature extraction unit is based on the Generalized Hebbian Algorithm (GHA). This work presents an architecture that shares one calculation unit across all channels, which minimizes area cost and power consumption greatly.

The circuit is implemented on ASIC work flow, which gives extended flexibility on area and power adjustment. The circuit also incoporates clock gating technology so to lower power consumption by memory units.

Last in this paper we present a method for parameter choosing. Based on the parameters chosen, a detailed area and power analysis is given. An analysis on GHA performance is also presented, which proved GHA to be an efficient substitution to the well-known PCA algorithm.