# 對動態測試產生的同步序列之正規驗證的研究

 dc.contributor 黃冠寰 zh_TW dc.contributor Gwan-Hwan Hwang en_US dc.contributor.author 李彥佑 zh_TW dc.contributor.author Yan-You Li en_US dc.date.accessioned 2019-09-05T11:31:25Z dc.date.available 2009-7-25 dc.date.available 2019-09-05T11:31:25Z dc.date.issued 2009 dc.description.abstract 並行程式面臨非確定行為的問題：在相同的輸入下重複執行多次可能產生不同的同步事件序列和執行結果。這使得並行程式難以進行測試。對非確定行為的並行程式進行動態測試的常見方法是將受測的並行程式重複執行許多次。每次執行受測的並行程式會產生一個同步序列（SYN-sequences）。除了執行結果之外，我們通常還必須驗證搜集到的SYN-sequences以確保並行程式的行為滿足我們所要求的規格或需求。這篇論文的目標即在於驗證SYN-sequences。 我們提出了對SYN-sequence進行正規驗證的方法。首先，我們研究用以驗證SYN-sequences的規格或需求的表達法。根據SYN-sequence表達了同步事件間偏序關係的事實，我們採用temporal logic來表示規格。接下來的目標就是如何有效率的根據規格來驗證SYN-sequences。因此，我們發展了三種不同的方法來將SYN-sequence轉換成模型，然後就可以利用temporal logic做正規驗證。我們也探討了如何用適當的表達法表達規格，以及如何選擇合適的模型。實驗結果驗證了對SYN-sequence進行有效率的驗證是可行的。 zh_TW dc.description.abstract Concurrent programs exhibit nondeterministic behavior in that multiple executions thereof with the same input might produce different sequences of synchronization events and different results. It makes the concurrent programs difficult to test. Dynamic testing of a concurrent program with nondeterministic behavior usually involves multiple executions of the target concurrent program. Each execution of the target concurrent program produces a synchronization sequences or SYN-sequences. In addition to the execution results, we usually have to verify the collected SYN-sequences to make sure that the behavior of the concurrent program meets its specification or requirement. In this thesis, we target on how to verify the SYN-sequences. We propose a scheme for the formal verification of the SYN-sequence. First, we study how to express the specification or requirement which can be used to verify SYN-sequences. According to the fact that a SYN-sequence represents a partial order relationship of synchronization events, we employ the temporal logic to express the specification. Then, we target on how to efficiently verify SYN-sequences according to the specification. As a result, we develop three different methods to transfer the target SYN-sequence to models which can then be verified in temporal logic. We also discussed how to express the specifications in suitable expression types and how to choose an appropriate model. The experimental results show that a systematic verification of SYN-sequence is feasible. en_US dc.description.sponsorship 資訊工程學系 zh_TW dc.identifier GN0696470447 dc.identifier.uri http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22GN0696470447%22.&%22.id.& dc.identifier.uri http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/106737 dc.language 英文 dc.subject dynamic testing en_US dc.subject reachability testing en_US dc.subject formal verification en_US dc.subject model checking en_US dc.subject SYN-sequence en_US dc.title 對動態測試產生的同步序列之正規驗證的研究 zh_TW dc.title The Formal Verification of SYN-Sequences Generated in Dynamic Testing en_US

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