應用於第五代行動通訊之28 GHz與38 GHz之功率放大器研究

Abstract

第一個電路為利用變壓器功率合成技術之Ka頻帶之功率放大器，使用半圈之變壓器實現功率結合與阻抗轉換以達到節省晶片面積，在量測頻率28 GHz時，增益為10.13 dB，飽和輸出功率為21.69 dBm，OP1dB為16.48 dBm，最大功率附加效率Peak PAE為19.36 %，整體晶片佈局面積為0.29 mm2。 第二個電路為變壓器電流合成技術之Ka頻帶功率放大器，為了提升功率放大器的增益，採用二級功率放大器進行設計，再使用變壓器電流合成技術提升輸出功率，量測結果在28 GHz時增益為14.07 dB，飽和輸出功率為23.9 dBm，OP1dB為19.07 dBm，最高功率附加效率為13 %，晶片佈局面積為0.9 mm2。 第三個電路為利用直接並聯功率合成瓦級功率輸出之Ka頻帶功率放大器，為了達到高增益，透過三級放大器進行設計，並使用直接並聯功率合成提升輸出功率，量測結果在38GHz時增益為19.6 dB，飽和輸出功率為28.4 dBm，OP1dB為27.6 dBm，最高功率附加效率為22.92 %，整體晶片佈局面積為5.22 mm2。The first circuit is Ka-band power amplifier with transformer combining technique which use half-turn transformer to implement power combining and impedance transformations, and to reduce size of chip. The PA achieves measured small-signal gain (S21) of 10.13 dB and maximum saturation output power (Psat) of 21.69 dBm, the OP1dB of 16.48 dBm and peak power-added efficiency (PAE) is 19.36 % at 28 GHz. The chip area including is 0.29 mm2. The second circuit is Ka-band power amplifier using current combining transformer technique. In order to reach higher gain, this thesis use 2-stage power amplifier design, and use current combining technique to increase output power. The PA achieves measured S21 of 14.07 dB and Psat of 23.9 dBm, the OP1dB of 19 dBm and PAE of 13 % at 28 GHz. The chip area including is 0.9 mm2. The third circuit is Ka-band power amplifier using directly power combining technique. In order to reach higher gain, this thesis use 3-stage power amplifier design, and use directly power combining technique to increase output power. The PA achieves measured S21 of 19.6 dB and Psat of 28.4 dBm, the OP1dB of 27.6 dBm and PAE of 22.92 % at 238 GHz. The chip area including is 5.22 mm2.