在可程式化系統晶片中實現網路入侵偵測系統之高效能封包分類與比對電路

Abstract

本論文中所呈現的是在FPGA上實現一個非常有效率的header classification circuit，並且能夠運用於網路入侵偵測系統。Header classification circuit利用一些簡單的shift register與symbol encoder，即可以達到快速且精確的封包檔頭比對。並且與其他現有的電路做比較之後，顯示我們所設計的電路，運用於網路入侵偵測系統並且實作在FPGA上，可以符合高效率與低硬體資源消耗。

An efficient FPGA-based header classification circuit is proposed for network intrusion detection system (NIDS). The circuit is based on simple shift registers and symbol encoders for the fast packet header classification in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.