A 1-V 10.7MHz Fourth-Order Bandpass ΔΣ Modulators Using Two Switched Opamps
| dc.contributor | 國立臺灣師範大學電機工程學系 | zh_tw |
| dc.contributor.author | Chien-Hung Kuo | en_US |
| dc.contributor.author | Shen-Iuan Liu | en_US |
| dc.date.accessioned | 2014-10-30T09:28:40Z | |
| dc.date.available | 2014-10-30T09:28:40Z | |
| dc.date.issued | 2004-11-01 | zh_TW |
| dc.description.abstract | A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25- m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is 65 dBc below the desired signal. | en_US |
| dc.description.uri | http://ntur.lib.ntu.edu.tw/bitstream/246246/150205/1/54.pdf | zh_TW |
| dc.identifier | ntnulib_tp_E0610_01_004 | zh_TW |
| dc.identifier.issn | 0018-9200 | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32203 | |
| dc.language | en | zh_TW |
| dc.publisher | Institute of Electrical and Electronics Engineers�(IEEE) | en_US |
| dc.relation | IEEE J. Solid-State Circuits, 39(11), 2041-2045. | en_US |
| dc.title | A 1-V 10.7MHz Fourth-Order Bandpass ΔΣ Modulators Using Two Switched Opamps | en_US |