應用於多層堆疊之交錯型非揮發性記憶體選擇器
Abstract
設計並製作出一個Cross-point記憶體開關來整合於RRAM中，由於記憶體發展的趨勢為高密度、低耗能，而控制電晶體(一般來說是MOSFET)當需要減少元件的大小的時候將面臨問題，平面MOSFET的問題將妨礙記憶體的發展，因此考慮將平面結構發展成三維堆積的結構。
在製程上為求與RRAM上有最佳之相容性，傳統電晶體因製成溫度高，可能導致記憶體之良率下降，故選擇低溫製程之MIM結構並製作出元件,在目前製作出的元件能量測的，且MIM在VON在4V情況下，面積下最大寫入電流Iwrite電流密度約可達，且在絕緣層SiN厚度下在Sneak Path Leakage Effect中電流在寫入電壓Vwrite和Vwrite/2的比值已經達到，且MIM1比值可達，在實際的整合上，寄生電阻扣除後電流在Sneak Path Leakage Effect的比值會更高，目前已把NPN結構與RRAM記憶體結合，未來目標與MIM整合將可提高此二極體的功能性及實用性，可成為未來高密度之3D非揮發性記憶體之控制單元。
In this project, we will design and fabricate a switch for cross-point RRAM applications, since the trend of the development for non-volatile memory is high density, low power consumption. The select devices have the issue for high density memory due to planar structure such as MOSFET. Therefore, the 3D structure will be a candidate for next generation NVM. In the process, in order to have the best compatibility with RRAM, because of traditional transistors made of high temperature, the yield may lead to memory decline, so choose low-temperature process of MIM structure and produce components. The minimum size for our technology node with devices realized. And in the case of Von in the maximum Ion current density in the areacan up to, and the thickness of the insulating SiN layer the ratio of Vwrite current and Vwrite/2 current has reached, MIM1 device can reach 103. In the actual integration, after allowing for the parasitic resistance in the Sneak Path Leakage Effect current ratio will be higher. We Integrate NPN structure with RRAM to array is working now, and our future work is that integrate NPN structure with RRAM to higher the usability, we look for the high functionality and density for the 3D non-volatile memory with this select device
In this project, we will design and fabricate a switch for cross-point RRAM applications, since the trend of the development for non-volatile memory is high density, low power consumption. The select devices have the issue for high density memory due to planar structure such as MOSFET. Therefore, the 3D structure will be a candidate for next generation NVM. In the process, in order to have the best compatibility with RRAM, because of traditional transistors made of high temperature, the yield may lead to memory decline, so choose low-temperature process of MIM structure and produce components. The minimum size for our technology node with devices realized. And in the case of Von in the maximum Ion current density in the areacan up to, and the thickness of the insulating SiN layer the ratio of Vwrite current and Vwrite/2 current has reached, MIM1 device can reach 103. In the actual integration, after allowing for the parasitic resistance in the Sneak Path Leakage Effect current ratio will be higher. We Integrate NPN structure with RRAM to array is working now, and our future work is that integrate NPN structure with RRAM to higher the usability, we look for the high functionality and density for the 3D non-volatile memory with this select device
Description
Keywords
Cross-point, RRAM, MIM, NPN, Sneak Path Leakage Effect, Cross-point, RRAM, MIM, NPN, Sneak Path Leakage Effect