適於多叢集Fuzzy C-Means分群演算法之硬體架構設計

Abstract

本論文提出一個適合在高叢集的Fuzzy c-means分群演算法硬體架構，同時對分群質量中心點和訓練向量作管線化架構(pipeline)，可以獲得更低的硬體資源消耗和更高的計算速度。此外，合併以往迭代更新權重矩陣(membership coefficient matrix)以及質量中心成為單一的更新步驟，可以避免使用大量的儲存空間。

最後本論文所提出的硬體架構會在以FPGA為基礎的可程式化系統晶片設計(System On a Programmable Chip，SOPC)之平台上作實際的效能測試。由實驗的結果可知，本架構具備較低的計算複雜度、較低的硬體資源複雜度以及更高的效能。

This paper presents a novel low-cost and high-performance VLSI architecture for fuzzy c-means clustering. In the architecture, the operations at both the centroid and data levels are pipelined to attain high computational speed while consuming low hardware resources. In addition, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. Experimental results show that the proposed solution is an effective alternative for cluster analysis with low computational cost and high performance.