應用於極座標發射機封包調變之延遲鎖定迴路建構脈波寬度調變器設計與實現

Abstract

近年來極座標發射機有關的文獻中，脈波寬度調變器(Pulse-Width Modulator, PWM)和三角積分調變器(Delta-Sigma Modulator, DSM)，皆有被提出使用在發射機前端的封包調變[1]-[4]。對於需要高解析和高線性調變器的寬頻通訊系統而言，DSM就必須提高其量化器的位元數，才能通過寬頻通訊規格，但整體發射機需要的功率放大器個數就會倍增。幸運的是，若提高PWM的操作頻率，其所造成的諧波雜訊可輕易的被後端帶通濾波器濾除，所需的功率放大器也可少於DSM。

本論文提出一個應用於封包調變之延遲鎖定迴路建構脈波寬度調變器。為了達到高解析高線性的需求，一個128個相位輸出的延遲鎖定迴路被用來組合出64種置中型脈波寬度變化。本論文提出一個循環式壓控延遲線來減少延遲元件的個數，使得所有的128個相位可以同時地輸出。藉由一個簡易計數器，我們可將所有相位分為上升區以及下降區，來產生所需的脈波寬度輸出。本論文提出之延遲鎖定迴路建構脈波寬度調變器使用台積電90奈米製程。其整體功率消耗為36.83 mW，操作頻率為92.16MHz，供應電壓為1.2V。In recent years, the pulse-width modulation (PWM) and delta-sigma modulation (DSM) are two popular approaches used for the front-end of the envelope modulator in traditional polar transmitters[1]-[4]. For the wide bandwidth modern communications, a high resolution and high linearity of modulator is needed. So, the DSM must increase the bits of quantizer to meet the specification, but it would make the design of post-PAs difficult to be realized. Fortunately, if the operational frequency of PWM could be appropriately increased, the annoying harmonic effect would be easily attenuated by the post-bandpass filter and the number of the post-PAs is less than DSM.

This thesis presents a DLL-based PWM for the envelope modulation of polar transmitters. For the requirements of high resolution and high linearity, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a cyclic voltage controlled delay line is presented in this thesis. The 128 output phases can be simultaneously produced by the 8-delay units of VCDL. A simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed DLL-based PWM is fabricated by TSMC 90nm 1P9M process. The power consumption is 36.83 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.