具有誤差回授架構的低功耗三階雜訊移頻逐次逼近式類比數位轉換器
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2025
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在現代數位電子裝置中，類比數位轉換器扮演著至關重要的角色。它們廣泛應用於各種領域，包括通訊、醫療設備、工業控制、儀器儀表和消費性電子產品等。隨著科技無止盡的發展和應用的擴大，對低功耗、高精度和面積小類比數位轉換器的需求也日益增長，因此，我們將以提高效能為目標來設計類比數位轉換器。本文提出了一個具有誤差回授架構的低功耗三階雜訊移頻逐次逼近式類比數位轉換器。此電路僅用一顆單位增益緩衝器，有效減少整體的功率消耗與面積成本。所使用的單位增益緩衝器採用了互補自偏壓差分放大器接成的單位增益緩衝器，不需額外的共模回授和偏壓電路。此外，由於所提出的架構採用單位增益緩衝器和以乒乓式操作的延遲元件來傳遞量化誤差，無需考慮電容之間的匹配程度。與傳統的積分器比較起來，會有較佳的訊號準確度。此電路採用TSMC 0.18-μm 1P6M CMOS製程技術製作，所實現的晶片核心面積為0.417×0.669 mm2。此電路在2-MHz的取樣頻率及20-kHz的頻寬下，測得的最佳SNDR值為85.17 dB，相當於13.86-bit的ENOB。所提出的ADC在1.8-V電源電壓下的功率消耗為75.5 μW。FoMs為169.43 dB，FoMw為126.53 fj/Conv.。
In modern digital electronic devices, analog-to-digital converters (ADCs) play a crucial role. They find widespread use in numerous sectors, including communications, medical equipment, industrial control, instrumentation, and consumer electronics. With advancing technology and expanding application areas, there is an increasing demand for ADCs that are low power, high precision, and compact. Therefore, we aim to enhance ADCs focusing on low power consumption, high precision, and small footprint.This paper presents a low-power third-order noise-shaping SAR ADC with an error feedback architecture. The circuit uses only one unity-gain buffer, effectively reduce overall power consumption and area cost. The employed unity-gain buffer is a complementary self-biased differential amplifier (CSDA), eliminating the need for additional common-mode feedback and bias circuits. Moreover, since the proposed architecture employs unity gain buffers and delay elements operating in a ping-pong manner to deliver the quantization error, there is no need to consider the matching degree between capacitors. Compare with traditional integrators, there will be better signal accuracy.The proposed ADC fabricated in TSMC’s 0.18-μm 1P6M CMOS process technology, with a chip core area of 0.417×0.669 mm². It achieves an optimal SNDR of 85.17 dB at a sampling frequency of 2 MHz and a bandwidth of 20 kHz, corresponding to an ENOB of 13.86-bits. The power consumption of the proposed ADC at a 1.8-V supply voltage is 75.5 μW. The FoMs is 169.43 dB, and the FoMw is 126.53 fj/Conv..
In modern digital electronic devices, analog-to-digital converters (ADCs) play a crucial role. They find widespread use in numerous sectors, including communications, medical equipment, industrial control, instrumentation, and consumer electronics. With advancing technology and expanding application areas, there is an increasing demand for ADCs that are low power, high precision, and compact. Therefore, we aim to enhance ADCs focusing on low power consumption, high precision, and small footprint.This paper presents a low-power third-order noise-shaping SAR ADC with an error feedback architecture. The circuit uses only one unity-gain buffer, effectively reduce overall power consumption and area cost. The employed unity-gain buffer is a complementary self-biased differential amplifier (CSDA), eliminating the need for additional common-mode feedback and bias circuits. Moreover, since the proposed architecture employs unity gain buffers and delay elements operating in a ping-pong manner to deliver the quantization error, there is no need to consider the matching degree between capacitors. Compare with traditional integrators, there will be better signal accuracy.The proposed ADC fabricated in TSMC’s 0.18-μm 1P6M CMOS process technology, with a chip core area of 0.417×0.669 mm². It achieves an optimal SNDR of 85.17 dB at a sampling frequency of 2 MHz and a bandwidth of 20 kHz, corresponding to an ENOB of 13.86-bits. The power consumption of the proposed ADC at a 1.8-V supply voltage is 75.5 μW. The FoMs is 169.43 dB, and the FoMw is 126.53 fj/Conv..
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誤差回授, 雜訊移頻逐次逼近暫存式類比數位轉換器, 互補自偏壓差分放大器接成的單位增益緩衝器, 單位增益緩衝器, 低功耗, Error-feedback, Noise-shaping SAR ADC, CSDA, Unity gain buffer, Low Power