結合JTAG與8051之電路模擬器設計與實作

Abstract

本論文為8051微處理器與擴充式JTAG(Joint Test Action Group)硬體架構做結合，利用硬體描述語言(Hardware Description Language, HDL)，實現具有硬體除錯功能之8位元微處理器，並下載至Xilinx SPARTAN SP3C400的FPGA(Field Programmable Gate Array)晶片上，再搭配電腦上所開發的除錯介面軟體對硬體功能做驗證。JTAG技術已被廣泛應用，本研究實做此架構，並找出快速對硬體功能驗證的方法與減少軟體除錯的時間。

The purpose of this thesis is to combine 8051 microprocessor with extensible JTAG hardware architecture. We use VHDL to achieve 8 bits processor with hardware debugging and then download it to FPGA chip of Xilinx SPARTAN SP3C400. The hardware function is tested by debug interface software. JTAG technology has been applied widely and we operate this architecture in this study. It is our expectation to find rapid ways of testing hardware function and to reduce the time for debugging.