奈米級結構陣列製作技術應用於高效能電池元件之研製
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Date
2008-10-24
Authors
楊啟榮
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Abstract
本計劃提出結合自組裝奈米球微影(self-assembednanospherelithography,SANL)以及光輔助電化學蝕刻(photo-assistedelectrochemicaletching,PAECE)兩項技術，在矽晶片表面製作高深寬比的奈米孔洞陣列結構，並用於降低矽晶片的反射效率。實驗結果顯示SANSL能於矽晶片上定義出完整排列的陣列圖形。所完成的奈米級孔洞陣列結構，其蝕刻深度約為6.2μm，直徑約為90nm，即孔洞的深寬比可達約68:1。調變蝕刻電壓可以使奈米級孔洞陣列，轉變成奈米柱狀陣列結構，而當使用2V的蝕刻電壓時，能夠產生高度1μm，直徑為100nm，深寬比為10:1的奈米柱狀陣列。矽晶片表面經過粗化(texture)處理後可降低晶片表面的反射率，以增加矽質太陽能電池的發電效率。在200nm-890nm波長範圍內矽晶片的平均加權反射率為40.2%。未經過SANSL而只經過5分鐘的PAECE蝕刻後，加權平均反射效率降低為5.16%；然而，經過SANSL以及5分鐘的PAECE蝕刻後，加權平均反射效率可降低為1.73%。此外，當奈米級孔洞陣列結構表面再鍍上200Å的siliconnitride後，加權平均反射率可更進一步降低為0.878%。本論文所提出的新型製程技術，除具有低成本優勢外，所完成的奈米級孔洞陣列結構更可實際應用於單晶矽太陽能電池之抗反射結構。
This study presents the integration ofself-assembled nanosphere lithography (SANSL)and photo-assisted electrochemical etching(PAECE) to fabricate a nanostructure array witha high aspect ratio on the surface of siliconwafer, to reduce its reflectance. Theexperimental results show that the etching depthof the fabricated nanopore array structure isabout 6.2 μm and its diameter is about 90 nm,such that the aspect ratio of the pore can reachabout 68:1. Tuning the etching voltage canconvert the nanopore array to a nanopillar array.PAECE at 2 V can yield an array of nanopillarwith a height of 2 μm, a diameter of 100 nm andan aspect ratio of 10:1.After the surface of a silicon wafer hasbeen texturized, the reflectance of the wafersurface can be reduced to increase the powergeneration efficiency of a silicon-based solarcell. The weighted mean reflectance of a blanksilicon wafer is 40.2 % in the wavelength rangeof 280~890 nm. Five-minute PAECE withoutSANSL reduces the weighted mean reflectanceto 5.16 %. Five-minute PAECE with SANSLreduces the weighted mean reflectance to 1.73%. Further coating of a 200 Å-thick siliconnitride layer on the surface of a nanostructurearray reduces the weighted mean reflectanceeven to 0.878 %. The novel fabricationtechnology proposed in this study has theadvantage of being low cost, and the fabricatednanostructure array can be employed as anantireflection structure in single crystalline silicon solar cells.
This study presents the integration ofself-assembled nanosphere lithography (SANSL)and photo-assisted electrochemical etching(PAECE) to fabricate a nanostructure array witha high aspect ratio on the surface of siliconwafer, to reduce its reflectance. Theexperimental results show that the etching depthof the fabricated nanopore array structure isabout 6.2 μm and its diameter is about 90 nm,such that the aspect ratio of the pore can reachabout 68:1. Tuning the etching voltage canconvert the nanopore array to a nanopillar array.PAECE at 2 V can yield an array of nanopillarwith a height of 2 μm, a diameter of 100 nm andan aspect ratio of 10:1.After the surface of a silicon wafer hasbeen texturized, the reflectance of the wafersurface can be reduced to increase the powergeneration efficiency of a silicon-based solarcell. The weighted mean reflectance of a blanksilicon wafer is 40.2 % in the wavelength rangeof 280~890 nm. Five-minute PAECE withoutSANSL reduces the weighted mean reflectanceto 5.16 %. Five-minute PAECE with SANSLreduces the weighted mean reflectance to 1.73%. Further coating of a 200 Å-thick siliconnitride layer on the surface of a nanostructurearray reduces the weighted mean reflectanceeven to 0.878 %. The novel fabricationtechnology proposed in this study has theadvantage of being low cost, and the fabricatednanostructure array can be employed as anantireflection structure in single crystalline silicon solar cells.