用於逐次逼近式類比數位轉換器之高效能浮動開關電容技術設計

No Thumbnail Available

Date

2012

Authors

謝正恩
Cheng-En Hsieh

Journal Title

Journal ISSN

Volume Title

Publisher

Abstract

積體電路設計在現今製程技術的演進下,已開啟奈米時代。而製程精度的提升除了降低電路佈局的面積,驅使電路運作的電源電壓因而縮小,使得高效能與低功率的電路設計不斷產出。隨著可攜式電子產品高需求的帶動下,效能佳是現今產品發表的最基本門檻,反倒是輕薄短小以及電池的長時效性要求,逐漸成為電路設計之主流;特別是應用在人體或生物上的植入性醫學晶片,為了能達到永久使用不更換的最大目標,低功率對晶片的設計上,更是第一必備要件。在眾多的類比數位轉換器中,逐次逼近式類比數位轉換器(successive approximation register analog-to-digital converter, SAR ADC)最符合低功率的條件,在於其大部分的電路元件為數位邏輯所構成,以及每筆取樣資料的轉換過程中,僅需一顆比較器即可實現,這都大幅地縮減資料轉換所消耗的能源。然而,在製程技術逐年提升的影響下,具備較多數位電路的SAR ADC開始嶄露頭角,除了維持低功率的特色,也朝高速的電路設計方案邁進。 在本論文中,提出了浮動開關電容(floating capacitor switching, FCS)技術來降低電容式DAC的能量損耗,相較於傳統切換技術之DAC架構,所提出方法可有效的節省97.66%的平均能量損失。另外,在供應電壓0.9-V的操作下,結合FCS架構的電容切換方式,再提出了部分式浮動開關電容技術之差動SAR ADC,以及雙部分式浮動開關電容技術之單端SAR ADC的電路實現架構,並採用TSMC 0.18-μm 1P6M的標準製程完成,在奈式取樣頻寬的規格下,可達到的品質因數FOM值分別為21.7-fJ/conversion-step以及46.2-fJ/conversion-step。
With the development of modern CMOS fabrication, the integrated circuits had entered into the nanoscale. Smaller area and lower voltage design might be come true by the advanced processing. Hence, low-power with high-performance circuits had been presented constantly. Nowadays, the mainstream products trend of portable electronic devices, greatly chip performance is replaced by smaller, cheaper and long standby. In particular, low-power was an essential condition on the human body or biological implantable chip applications. All of analog-to-digital converter (ADC) types, successive approximation register (SAR) is appropriate for the low-power design by their much more digital circuits. Besides, the power dissipation can be significantly reduced by only one comparator which is needed to complete whole sampling data during each conversion phase. In addition, some of high speed circuits using SAR approach can be accomplished recently with the advanced process. In this thesis, seeking the comparison between a floating capacitor switching (FCS) scheme is proposed to reduce the energy consumption and conventional DAC approach, the proposed scheme can achieve 97.66% less average switching energy. Furthermore, the actuality architectures are realized by the partial FCS scheme based differential SAR ADC and double partial FCS scheme based single-ended SAR ADC at a 0.9-V supply voltage. Both of them were fabricated in the TSMC 0.18-μm 1P6M process technology. The presented SAR ADCs can achieve 21.7-fJ/conversion-step and 46.2-fJ/conversion-step figure of merit (FOM) in the Nyquist bandwidth, respectively.

Description

Keywords

類比數位轉換器, 逐次逼近暫存器, 電容式數位類比轉換電路, 浮動開關電容技術, 品質因數FOM, Analog-to-digital converter, successive approximation register, capacitive DAC array, floating capacitor switching (FCS), figure of merit (FOM)

Citation

Collections