A "Hybrid Sense" Algorithm for Layer Assignment in Three-Layer VLSI Routing

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dc.contributor.author張國恩zh_tw
dc.date.accessioned2014-10-27T15:26:48Z
dc.date.available2014-10-27T15:26:48Z
dc.date.issued1992-06-??zh_TW
dc.description.abstract佈局層指定（又稱可限性穿孔減少）是決定佈局中各線段的佈局層位置使得佈局所產生的穿孔數能儘量少。由於穿孔數的增加會降低電路之執行效益和增加電路製造成本，因此減少佈局中的穿孔是重要的。本文提出一個有效的演算法以減少三層佈局中的穿孔數。文中採用一種混合式的方式，並考慮實際設計上的限制問題，如端點限制與鄰接限制。這些問題皆有助於VLSI電路之製造。經過實驗證明，本混合式演算法是快速而有效的，並得到很好的結果。zh_tw
dc.description.abstractThe layer assignment, also called constrained via minimization, is to determine which layers can be used for routing the wire segments such that the number of vias can be minimized. Vias should be eliminated as many as possible in the layout design because vias will reduce the performance of the circuits and increase the manufacturing cost. In this paper, we present a heuristic algorithm to eliminate the vias in the three-layer routing instances using the hybrid sense method. Some associated constraints under practical considerations, such as restricted terminals and adjacent limitation, will be addressed and solved extensively. By our experiments, the algorithm is fast and efficient to generate very good solutions.en_US
dc.identifierF611F375-8FA1-ABEB-3A13-720B82FD0657zh_TW
dc.identifier.urihttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/17868
dc.language英文zh_TW
dc.publisher國立臺灣師範大學研究發展處zh_tw
dc.publisherOffice of Research and Developmenten_US
dc.relation(37)，243-265zh_TW
dc.relation.ispartof師大學報zh_tw
dc.titleA "Hybrid Sense" Algorithm for Layer Assignment in Three-Layer VLSI Routingzh-tw
dc.title.alternative有關三層VLSI佈局層指定的混合式演算法zh_tw

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