應用於極座標發射機封包調變之六位元置中型數位脈波寬度調變器的設計與實現

Abstract

在傳統的發射機應用中，常見的兩種封包調變器架構為三角積分調變器、與脈波寬度調變器。雖然DSM架構實現容易，但在LTE寬頻的要求下，多位元的輸出往往會增加後續PA在實現上的難度。PWM架構雖然有輸出諧波的困擾，但若能提高取樣操作頻率，及實現的脈波寬度線性度，其單位元的輸出將可大大降低PA實現的複雜度，解決諧波失真也只要在功率放大器後端增加帶通濾波器來濾除諧波失真。

為了提高脈波寬度調變器的信號線性度，我們將輸出的脈波置中對齊。相較於靠邊型PWM，置中型減少許多諧波失真，提高整體發射機效能。本論文以6位元置中型的PWM為例，其結果比靠邊型PWM有較佳的調變性能展現，而採用混合型的脈波寬度調變器架構，能減少不必要的延遲元件以及降低高速的計數器切換。

應用於LTE極座標發射器封包調變的脈波寬度調變器，設計全數位式置中混合型脈波寬度調變器。在所提出的調變器中，我們藉由延遲鎖定迴路所提供的128個相位，合成64種置中型脈波寬度的輸出，完成6 位元LTE信號的調變器要求。為了降低多重相位延遲鎖定迴路的延遲元件數目，我們使用一個簡單的計數器將相位輸出區分為上升及下降兩類。並將輸入脈波轉換成脈衝，以便環繞multi-phase VCDL來得到128個相位的輸出。最後經由多工器的選取，以及邊緣合成器合成64種寬度的置中型脈波。本論文採用TSMC 90 nm 1P9M量測輸入92.16 MHz在1.2 V的電源電壓下，量測的功率為22.05mW，而使用TSMC 90nm GUTM 模擬結果在122.88 MHz供應電壓為1 V以下，功率為30.82mW。The pulse-width modulation (PWM) and delta-sigma modulation (DSM) are two popular approaches used for the realization of the envelope modulator in traditional polar transmitters. Although DSM provides an easy structure for implementation, multi-bit outputs due to the requirements of linearity and wide bandwidth in modern communications would make the design of post-PAs difficult to be realized. Fortunately, if the operational frequency of PWM could be appropriately increased, the annoying harmonic effect would be easily attenuated by the post-bandpass filter.

In this thesis, a hybrid digital PWM (DPWM) having counter and delay cells is devised to compromise between area cost and operational speed. To increase the linearity of DPWM, the center-aligned pulse technology is adopted in the presented modulator. Sixty-four different pulse widths of outputs corresponding to the 6-bit input signal are designed in the presented modulator. The center-aligned output pulses exhibits lower noise floor near the interest band than the edge-aligned counterpart.

This thesis presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is measured in TSMC 90nm 1P9M RF process. The power consumption is 22.05 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2 V, and the other simulated in TSMC 90nm 1P9M GUTM process. The power consumption is 36.82 mW at a 122.88 MHz input reference frequency and a supply voltage of 1 V.