應用於衛星通訊與Wi-Fi 7之壓控振盪器設計
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2025
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近年來,隨著無線通訊技術的蓬勃發展與半導體製程的不斷進步,系統的運作頻率也逐步提升,使得高頻積體電路(IC)的設計變得尤為重要。無論是數位訊號處理還是射頻應用,都需要一個穩定且精確的時脈來源,以確保系統的正常運行。因此,時脈產生器在電路設計中扮演關鍵角色。本次論文以射頻收發系統中的本地振盪源為研究主軸,設計並實現了兩種不同應用頻段的時脈產生器,分別為應用於衛星頻帶共模諧振暨變壓器回授電壓控制振盪器以及應用於 WiFi – 7之逆Class-F 電壓控制振盪器。論文的第一部分實現了應用於衛星通訊基於共模諧振 (CMR) 暨變壓器回授 (TF)壓控振盪器 (VCO)。該設計採用 NMOS cross couple pair 並利用變壓器回授顯著提升輸出振幅,並透過共模諧振有效抑制閃爍雜訊 (flicker noise) 的上轉換效應。為進一步改善相位雜訊性能,採用自偏壓開關電容陣列 (SB-SCA) 以提升諧振槽之品質因數 (Q-factor)。該 VCO 採用 90 奈米 CMOS 製程實現,量測之頻率調諧範圍達 15%,涵蓋 11.5 至 13 GHz。在 1 MHz 頻率偏移處,本設計達成 -115.7 dBc/Hz 之相位雜訊表現,對應的性能指標(FoM)為189.1 dBc/Hz。該VCO功耗僅6.5 mW,核心面積僅0.065 mm²第二部分實現了一款應用於 Wi-Fi 7 之逆 Class-F 電壓控制振盪器(VCO)。該設計採用 PMOS 與 NMOS 組成 pseudo cross-coupled 對,以達成電流重用(current-reused)效果,進一步降低功耗。此外,為避免額外功耗損失,本設計未額外添加尾電流源(tail current source)來控制電流。振盪核心利用 LC 共振腔於閘極端(Gate)產生主要振盪頻率,並透過汲極端(Drain)於二、三次諧振點進行共振,以抑制閃爍雜訊(flicker noise)上升,進而提升相位雜訊表現。本設計採用 8-bit 開關電容陣列(SCA)來調節共振腔的等效電容值,以精細控制振盪頻率範圍。相較於傳統的變容二極體(varactor)調諧機制,SCA 透過離散電容切換,能有效降低調諧時的非線性效應,進一步提升共振腔的等效品質因數(Q-factor),進而改善 VCO 的相位雜訊與頻率穩定性,以滿足 Wi-Fi 7 之高效能通訊應用需求。
In recent years, the rapid advancement of wireless communication technologies and continuous improvements in semiconductor processes have led to an increase in system operating frequencies, making the design of high-frequency integrated circuits (ICs) increasingly critical. Whether in digital signal processing or radio-frequency (RF) applications, a stable and precise clock source is essential to ensure proper system functionality. Therefore, clock generators play a pivotal role in circuit design. This thesis focuses on the design and implementation of local oscillators (LOs) for RF transceiver systems, realizing two clock generators for different application bands: a common-mode resonance (CMR) and transformer-feedback (TF) voltage-controlled oscillator (VCO) for satellite communication and an inverse Class-F VCO for Wi-Fi 7 applications.The first part of this thesis presents the design and implementation of an VCO based on common-mode resonance (CMR) and transformer feedback (TF) for satellite communication. The proposed design employs an NMOS cross-coupled pair with transformer feedback to significantly enhance the output swing. Meanwhile, the CMR architecture effectively suppresses the flicker noise up-conversion effect, which is critical for phase noise performance. To further improve the Q-factor of the resonator, a self-biased switched capacitor array (SB-SCA) is incorporated, enhancing the overall phase noise characteristics. Fabricated using a 90-nm CMOS process, the measured frequency tuning range achieves 15%, covering 11.5 to 13 GHz. The measured phase noise at a 1 MHz offset is −115.7 dBc/Hz, corresponding to a figure of merit (FoM) of 189.1 dBc/Hz. This VCO consumes only 6.5 mW of power and occupies a compact core area of 0.065 mm².The second part of this thesis presents the design and implementation of an inverse Class-F23 VCO for Wi-Fi 7 applications. The proposed design adopts a pseudo cross-coupled structure comprising PMOS and NMOS transistors to achieve a current-reused topology, effectively reducing power consumption. Additionally, to minimize unnecessary power dissipation, the design eliminates the conventional tail current source, preventing additional current losses. The oscillation core leverages an LC resonator at the gate terminal to generate the fundamental oscillation frequency, while resonating at the second and third harmonic frequencies at the drain terminal to suppress flicker noise up-conversion, thereby improving phase noise performance. Furthermore, an 8-bit switched capacitor array (SCA) is employed to finely tune the equivalent capacitance of the resonator, allowing precise frequency control. Compared to traditional varactor-based tuning mechanisms, the discrete capacitor switching approach of the SCA effectively mitigates nonlinear tuning effects, further enhancing the Q-factor of the resonator. This optimization significantly improves both phase noise and frequency stability, making the proposed VCO a highly suitable candidate for high-performance Wi-Fi 7 communication applications.
In recent years, the rapid advancement of wireless communication technologies and continuous improvements in semiconductor processes have led to an increase in system operating frequencies, making the design of high-frequency integrated circuits (ICs) increasingly critical. Whether in digital signal processing or radio-frequency (RF) applications, a stable and precise clock source is essential to ensure proper system functionality. Therefore, clock generators play a pivotal role in circuit design. This thesis focuses on the design and implementation of local oscillators (LOs) for RF transceiver systems, realizing two clock generators for different application bands: a common-mode resonance (CMR) and transformer-feedback (TF) voltage-controlled oscillator (VCO) for satellite communication and an inverse Class-F VCO for Wi-Fi 7 applications.The first part of this thesis presents the design and implementation of an VCO based on common-mode resonance (CMR) and transformer feedback (TF) for satellite communication. The proposed design employs an NMOS cross-coupled pair with transformer feedback to significantly enhance the output swing. Meanwhile, the CMR architecture effectively suppresses the flicker noise up-conversion effect, which is critical for phase noise performance. To further improve the Q-factor of the resonator, a self-biased switched capacitor array (SB-SCA) is incorporated, enhancing the overall phase noise characteristics. Fabricated using a 90-nm CMOS process, the measured frequency tuning range achieves 15%, covering 11.5 to 13 GHz. The measured phase noise at a 1 MHz offset is −115.7 dBc/Hz, corresponding to a figure of merit (FoM) of 189.1 dBc/Hz. This VCO consumes only 6.5 mW of power and occupies a compact core area of 0.065 mm².The second part of this thesis presents the design and implementation of an inverse Class-F23 VCO for Wi-Fi 7 applications. The proposed design adopts a pseudo cross-coupled structure comprising PMOS and NMOS transistors to achieve a current-reused topology, effectively reducing power consumption. Additionally, to minimize unnecessary power dissipation, the design eliminates the conventional tail current source, preventing additional current losses. The oscillation core leverages an LC resonator at the gate terminal to generate the fundamental oscillation frequency, while resonating at the second and third harmonic frequencies at the drain terminal to suppress flicker noise up-conversion, thereby improving phase noise performance. Furthermore, an 8-bit switched capacitor array (SCA) is employed to finely tune the equivalent capacitance of the resonator, allowing precise frequency control. Compared to traditional varactor-based tuning mechanisms, the discrete capacitor switching approach of the SCA effectively mitigates nonlinear tuning effects, further enhancing the Q-factor of the resonator. This optimization significantly improves both phase noise and frequency stability, making the proposed VCO a highly suitable candidate for high-performance Wi-Fi 7 communication applications.
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壓控振盪器, 變壓器回授, 共模諧振, 電流重用, 逆 Class-F (Class F23)振盪器, Ku頻段, 衛星通訊, 閃爍雜訊, Wi-Fi 7, Voltage-Controlled Oscillator (VCO), Transformer Feedback, Common-Mode Resonance (CMR), Current-Reused, Inverse Class-F23 Oscillator, Satellite Communication, Ku-band, Wi-Fi 7, Flicker Noise