具備防止誤觸發機制之低漏電流靜電放電箝制電路
| dc.contributor | 蔡政翰 | zh_TW |
| dc.contributor | 林群祐 | zh_TW |
| dc.contributor | Tsai, Jeng-Han | en_US |
| dc.contributor | Lin, Chun-Yu | en_US |
| dc.contributor.author | 陳柏孝 | zh_TW |
| dc.contributor.author | Chen, Po-Xiao | en_US |
| dc.date.accessioned | 2024-12-17T03:22:25Z | |
| dc.date.available | 2026-08-01 | |
| dc.date.issued | 2024 | |
| dc.description.sponsorship | 電機工程學系 | zh_TW |
| dc.identifier | 61175057H-45439 | |
| dc.identifier.uri | https://etds.lib.ntnu.edu.tw/thesis/detail/ce028a612e2914b99f178e468946dae0/ | |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/122944 | |
| dc.language | 英文 | |
| dc.title | 具備防止誤觸發機制之低漏電流靜電放電箝制電路 | zh_TW |
| dc.title | Low-Leakage Power-Rail ESD Clamp Circuit with False Trigger Prevention Mechanism | en_US |
| dc.type | 學術論文 |