K頻帶互補式金氧半功率放大器設計

Abstract

第一個電路為變壓器功率結合技術之K頻帶功率放大器，採用半圈變壓器 (Half-turn Transformer)實現功率結合與阻抗轉換以達到節省面積，量測結果在23.5 GHz時，增益為12 dB，飽和輸出功率(P_sat)為22.5 dBm，1dB增益壓縮輸出功率(OP_1dB)為18.1 dBm，最高功率輔助效率(PAE)為21.8%，晶片佈局面積為0.29 mm^2。 第二個電路為變壓器電流結合技術之K頻帶功率放大器，延續第一個設計之功率放大器，運用變壓器電流結合技術(Current Combining Transformer)來提升輸出功率，將功率放大單元直接並聯在進行匹配，而為了要提高增益，採用兩級功率放大器進行設計，量測結果在23 GHz時，增益為19.5 dB，飽和輸出功率(P_sat)為24.9 dBm，1 dB增益壓縮輸出功率(OP_1dB)為20.6 dBm，最高功率輔助效率(PAE)為17.0%，晶片佈局面積為0.97 mm^2。

The first circuit is K-band power amplifier with transformer combining technique which uses half-turn transformer to implement power combining and impedance transformations, and to reduce size of chip. The PA achieves measured small-signal gain ("S" _"21" ) of 12 dB and maximum saturation output power ("P" _"sat" ) of 22.5 dBm, the measured output 1-dB compression point (〖"OP" 〗_"1dB" ) of 18.1 dBm and peak power-added efficiency (PAE) is 21.8 % at 23.5 GHz. The chip area is 0.29 mm^2. Recall that in first design, the second circuit is power amplifier using current combining transformer technique to increase output power. In order to reach higher gain, this thesis use 2-stage power amplifier design. The PA achieves measured "S" _"21" of 19.5 dB and "P" _"sat" of 24.9 dBm, the 〖"OP" 〗_"1dB" of 20.6 dBm and PAE of 17 % at 23 GHz. The chip area including is 0.97 mm^2.