C頻帶互補式金屬氧化物半導體功率放大器與線性化技術研究

Abstract

第一顆電路為使用變壓器功率合成技術之C頻段功率放大器，以變壓器功率合成技術完成放大器功率結合，並藉由阻抗轉換特性達成輸出與輸入之阻抗匹配。當操作頻率為5.3 GHz且VG1為0.85 V時，功率增益約16.48 dB，飽和輸出功率(Psat)約為27.69 dBm，1-dB增益壓縮點之輸出功率(OP1dB)約為22.53 dBm，最大功率附加效率(PAE)約為28.34 %。整體晶片佈局面積為1.17 mm × 0.655 mm。 第二顆電路為具內建線性器之C頻段功率放大器，線性器架構採用共閘極串級二極體組態。當操作頻率為5.3 GHz，且VG1為1 V線性器開啟時，功率增益約14.25 dB，飽和輸出功率(Psat)約為27.06 dBm，1-dB增益壓縮點之輸出功率(OP1dB)從22.48 dBm提升至26.24 dBm，最大功率附加效率(PAE)約為23.94 %，三階交互調變失真IMD3在輸出功率約為18 dBm以前皆可抑制在-40 dBc左右。整體晶片佈局面積為1.14 mm × 0.64 mm。 第三顆電路為具內建線性器之C頻段功率放大器，線性器架構採用疊階組態。當操作頻率為5.3 GHz ，且VG1為0.85 V線性器開啟時，功率增益約11.98 dB，飽和輸出功率(Psat)約為26.84 dBm，1-dB增益壓縮點之輸出功率(OP1dB)從 22.69 dBm提升至24.7 dBm，最大功率附加效率(PAE)約為22.22 %，而三階交互調變失真IMD3在輸出功率約為18.5 dBm以前皆可抑制在-40 dBc左右。整體晶片佈局面積為1.14 mm × 0.64 mm。 第四顆電路為具內建線性器之C頻段功率放大器，線性器架構採用共閘極串級電阻組態。當操作頻率為5.3 GHz ，且VG1為0.85 V線性器開啟時，功率增益約13.1 dB，飽和輸出功率(Psat)約為26.94 dBm，1-dB增益壓縮點之輸出功率(OP1dB)從20.95 dBm提升至23.81 dBm，最大功率附加效率(PAE)約為25.05 %，而三階交互調變失真IMD3在輸出功率約為18.5 dBm以前皆可抑制在-40 dBc左右。整體晶片佈局面積為1.14 mm × 0.64 mm。

The first circuit is power amplifier, operating at C-band, and using transformer combination technology to combine output power from two way amplifiers. And it can also convert characteristic impedance at both input and output. When the circuit operates at 5.3 GHz and VG1 is 0.85 V, the power gain is about 16.48 dB, and saturation output power (Psat) is about 22.34 dBm, 1 dB output power compression point (OP1dB) is about 22.53 dBm, and the maximum power-added efficency (PAE) is about 28.34%. The overall chip size is 1.17 mm × 0.655 mm. Second circuit is power amplifier with built-in linearizer, operating at C-band, the frame of linearizer is using common gate cascade diode configuration. When the circuit with linearizer operates at 5.3 GHz, VG1 is 1V, the power gain is about 14.25 dB, saturation output power (Psat) is about 27.06 dBm, 1 dB output power compression point (OP1dB) increased from 22.48 dBm to 26.24 dBm, and the maximum power-added efficency (PAE) is about 23.94%, and third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 18 dBm. The overall chip size is 1.14 mm × 0.64 mm. Third circuit is power amplifier with built-in linearizer, operating at C-band, the frame of linearizer is using cascode configuration. When the circuit with linearizer operates at 5.3 GHz, VG1 is 0.85 V, the power gain is about 11.98 dB, saturation output power (Psat) is about 26.84 dBm, 1 dB output power compression point (OP1dB) increased from 22.69 dBm to 24.7 dBm, and the maximum power-added efficency (PAE) is about 22.22%, and third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 18.5 dBm. The overall chip size is 1.14 mm × 0.64 mm. Last circuit is power amplifier with built-in linearizer, operating at C-band, the frame of linearizer is using common gate cascade resistance configuration. When the circuit with linearizer operates at 5.3 GHz, VG1 is 0.85 V, the power gain is about 13.1 dB, saturation output power (Psat) is about 26.94 dBm, 1 dB output power compression point (OP1dB) increased from 20.95 dBm to 23.81 dBm, and the maximum power-added efficency (PAE) is about 25.05%, and third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 18.5 dBm. The overall chip size is 1.14 mm × 0.64 mm.