內嵌CMOS 影像感測擷取模組及影像濾波器之FPGA 平台設計
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2004
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Abstract
隨著影像感應晶片的製成技術進步，未來電子、資訊產品也將漸漸把
影像服務視為基本配備，例如：數位相機、視訊會議、玩具…等等。目前
影像感應晶片的製程方式分為CCD 與CMOS 兩類，由於CMOS 影像感
測晶片限於材料特性限制，影像品質一直略遜於CCD 影像感測晶片，若
使用軟體改善CMOS 影像感測晶片的影像品質，將造成系統速度變慢，
若採用額外的處理器，使得成本提升皆不划算。因此提出整合CMOS 影
像感測晶片之”擷取影像”與”影像濾波” FPGA 發展平台。藉由FPGA 硬體
的速度，可同時擷取影像並選擇進行線性(高通、低通與高斯平滑濾波)或
非線性(最大值、中值與最小值濾波)，將雜訊予以濾除。
在線性濾波器方面，改善了Crookes 影像濾波器的設計，使其能以較
少的硬體資源達成濾波效果，及充分配合FPGA 內建的Block RAM 做成
動態大小的佇列，使得濾波器能即時地適應不同尺寸的影像大小。非線性
的排序濾波器，則採Maheshwari 演算法為基礎，並提出與線性濾波器共
用部分資源的方式，以減輕資體資源的花費。
CMOS image sensors become more and more widely used today in toys, mobile-phones, and digital cameras. As far as speed and image qualities are concerned CCD image sensors are still superior to CMOS image sensors and are more expensive. This paper presents a FPGA version to improve CMOS image sensor performance. The ever increasing gate-count in a FPGA Chip has made it possible to integrate the image capturing and filtering processes into a hardware circuitry, providing a faster image capturing as well as noise filtering. Therefore, this project proposed a CMOS image sensor application of FPGA platform design that integrated the image capturing and many noise filtering circuits, such as low pass, High pass, mean, maximum, minimum, ect., which were selectable through different parameter setting. This FPGA chip can communicate with a pipelined RAM structure to process the capturing images and to enhance their qualities. Actual hardware design in this paper has made FPGA consumption very effective by carefully rearranged the buffers and processor elements(PEs) in Crooks’ linear filter, two third of the original registers can be saved. Also by modified Maheshwari’s nonlinear filter with sharing buffers, the buffer area is again reduced the half of the original size. According to the preliminary test, the hardware image capturing circuit in the FPGA might have several ten times faster than usually done by microprocessors (pic, 89c51 series) or by DSP chips that could demonstrate more favorable real time performance.
CMOS image sensors become more and more widely used today in toys, mobile-phones, and digital cameras. As far as speed and image qualities are concerned CCD image sensors are still superior to CMOS image sensors and are more expensive. This paper presents a FPGA version to improve CMOS image sensor performance. The ever increasing gate-count in a FPGA Chip has made it possible to integrate the image capturing and filtering processes into a hardware circuitry, providing a faster image capturing as well as noise filtering. Therefore, this project proposed a CMOS image sensor application of FPGA platform design that integrated the image capturing and many noise filtering circuits, such as low pass, High pass, mean, maximum, minimum, ect., which were selectable through different parameter setting. This FPGA chip can communicate with a pipelined RAM structure to process the capturing images and to enhance their qualities. Actual hardware design in this paper has made FPGA consumption very effective by carefully rearranged the buffers and processor elements(PEs) in Crooks’ linear filter, two third of the original registers can be saved. Also by modified Maheshwari’s nonlinear filter with sharing buffers, the buffer area is again reduced the half of the original size. According to the preliminary test, the hardware image capturing circuit in the FPGA might have several ten times faster than usually done by microprocessors (pic, 89c51 series) or by DSP chips that could demonstrate more favorable real time performance.
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Keywords
CMOS 影像感測器, 迴旋運算器, 空間濾波器, 心臟壓縮式陣列, 硬體排序器, 現場式可程式閘陣列