應用於音頻頻帶數位類比轉換器的24位元低成本、高效率插值濾波器和三角積分調變器

Abstract

本論文提出了應用於音頻數位類比轉換器的24位元低成本、高效率插值濾波器和三角積分調變器。在插值濾波器中，我們採用凱薩窗函數來設計具有較少硬體的線性相位半頻帶有限脈衝響應濾波器，除了能有相對較少的濾波器階數外，還能加大頻帶外的阻帶衰減率，並抑制鏡像雜訊。此外，利用多工器來減少大量的加法器，改善使用多相位折疊架構具有加法器數量與濾波器階數成正比的缺點。在三角積分調變器中，使用2+2 SMASH架構來確保高階三角積分調變器的穩定。採用訊號處理電路來節省輸入至第二級電路前的多位元減法器，並於第二級採用硬體成本較低的量化誤差回授架構，改善SMASH架構在硬體成本上的缺點。 本研究提出的電路架構使用TSMC 0.18-um 1P6M CMOS技術實現，總耗費的核心面積為0.35 mm2。在24 kHz的頻帶下，測得的SNR為143.91 dB，且在1.8 V的電源電壓下，測得功率消耗為3.14 mW。此外，利用Altera Cyclone IV GX型號的FPGA開發板進行驗證，從量測的結果顯示，在24 kHz的頻帶下，測得的效能與post-sim相同。總共使用的邏輯數目(LEs)為3697。在1.2 V的電源電壓下，測得的功率消耗為0.93 mW。This paper presents a 24-bit, low-cost, high-efficiency interpolation filter and delta-sigma modulator for audio digital-to-analog converters (DACs). In the interpolation filter, we employ a Kaiser window function to design a linear-phase, half-band finite impulse response (FIR) filter with reduced hardware complexity. This design not only reduces the number of filter stages but also increases the stopband attenuation beyond the passband, effectively suppressing image noise. Additionally, we utilize multiplexers to reduce a large number of adders, addressing the drawback of the polyphaser-folded architecture where the number of adders is proportional to the filter stages. In the delta-sigma modulator, a 2+2 SMASH architecture is used to ensure stability for higher-order delta-sigma modulator. Signal processing circuits are employed to save multi-bit subtractors before the second stage, and a error feedback structure with lower hardware cost is implemented in the second stage to address the hardware cost limitation of the SMASH architecture. The proposed architecture in this study was implemented using TSMC 0.18-um 1P6M CMOS technology, with a total core area of 0.35 mm2. In the 24 kHz bandwidth, the measured SNR was 143.91 dB, and the power consumption was measured at 3.14 mW with a supply voltage of 1.8 V. Furthermore, verification was performed using an Altera Cyclone IV GX model FPGA development board, and the measured performance in the 24 kHz bandwidth matched the post-simulation results. The total number of used logic elements (LEs) was 3697. At a supply voltage of 1.2 V, the measured power consumption was 0.93 mW.