元件層級及系統層級之靜電放電防護設計
| dc.contributor | 林群祐 | zh_TW |
| dc.contributor | Lin, Chun-Yu | en_US |
| dc.contributor.author | 傅偉豪 | zh_TW |
| dc.contributor.author | Fu, Wei-Hao | en_US |
| dc.date.accessioned | 2019-09-03T10:45:46Z | |
| dc.date.available | 2020-07-30 | |
| dc.date.available | 2019-09-03T10:45:46Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | 隨著製程演進，積體電路中電晶體尺寸逐漸縮小，靜電放電 (ESD) 容易造成晶片內部不可逆之破壞，因此積體電路產品中靜電放電防護的可靠度議題必須被深入探討。 現今的積體電路在出廠時需要做元件層級的靜電放電測試，當積體電路安裝在電子產品後，又需要做系統層級的靜電放電測試。因系統層級靜電放電的測試規範 (IEC 61000-4-2) 的嚴格要求，積體電路產品常通過了元件層級靜電放電的測試標準，也可能無法達到系統層級的靜電放電的標準，因此本論文進行元件層級和系統層級的靜電放電防護研究。 在論文第二章使用雙極性電晶體 (BJT)、二極體 (diode)、閘極接地N型金屬氧化物半導體場效電晶體 (GGNMOS)、靜電放電箝制 (power clamp) 作為靜電放電防護電路的研究基礎，並在0.18um 1.8 V 的 Bi CMOS製程下實現。這些防護電路使用傳輸線觸波產生器 (TLP) 系統、人體放電模式 (HBM) 儀器、靜電槍 (ESD gun) 進行測試，測試結果證明二極體和靜電放電箝制有較好的元件層級的防護能力。瞬態電壓抑制 (TVS) 二極體被用來提升系統層級的靜電放電防護能力。 在論文第三章提出了一項創新使用二極體串嵌入式矽控整流器 (DSESCR) 之靜電放電防護元件，因傳統式的二極體串聯 (TDS) 和 改善型二極體串 (IDS) 有較高箝制電壓及高漏電流，故DSESCR被用來改善缺點。此元件在0.18um 1.8 V 的 CMOS製程下實現。這些防護電路使用TLP系統、HBM 儀器、ESD gun進行測試，測試結果證明能有效改善漏電過大及箝制電壓過大的缺點。 本論文第二章及第三章所設計的元件，可以依其特性應用在各種的電路上，能夠有效的防護內部電路。 | zh_TW |
| dc.description.abstract | With the continuous evolution of semiconductor integrated circuits (ICs) process, electrostatic discharge (ESD) events are likely to cause IC products suffered irreversible damage. All microelectronic products must meet the reliability specifications. Therefore, ESD must be taken into consideration. Nowadays, when the IC chip is produced, it must test the robustness of component-level ESD. When the IC chip is mounted on the electronics products, it also needs to test the robustness of system-level ESD. The component-level and system-level ESD qualifications are needed to test based on a set of corresponding standardization documents. System-level ESD is an increasingly important reliability issue in CMOS IC products. It has been also reported that reliability issues still exist in CMOS ICs under system-level ESD tests, even though IC products have passed component-level ESD specifications. Therefore, the component-level and system-level ESD robustness are analyzed in this thesis. In chapter 2, the ESD protection circuits of bipolar junction transistor (BJT), diode, gate-grounded NMOS (GGNMOS), and power clamp are studied. These ESD protection circuits have been fabricated in 0.18-μm 1.8V BiCMOS process. The transmission-line-pulsing (TLP) system, human-body-model (HBM), and ESD gun are used to verify ESD protection circuits. The experimental results of diodes and power clamp show better component-level ESD robustness. Transient-voltage-suppression (TVS) diode is used to improve the system-level ESD robustness. In chapter 3, a novel design of diode string with embedded silicon-controlled rectifier (DSESCR) device is proposed for ESD protection. The traditional diode string (TDS) and improved diode string (IDS) have drawbacks of a high clamp voltage and a high leakage current, so DSESCR is proposed to improve these drawbacks. These ESD protection circuits have been fabricated in 0.18-μm 1.8V CMOS process. The TLP system, HBM, and ESD gun are used to verify IDS and DSESCR device. DSESCR can improve the clamp voltage and leakage current. In chapter 2 and chapter 3, according to their characteristics of the ESD protection devices, the devices can be used to protect different internal circuits. | en_US |
| dc.description.sponsorship | 電機工程學系 | zh_TW |
| dc.identifier | G060375031H | |
| dc.identifier.uri | http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22G060375031H%22.&%22.id.& | |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/95659 | |
| dc.language | 英文 | |
| dc.subject | 雙極性電晶體 | zh_TW |
| dc.subject | 元件層級靜電放電 | zh_TW |
| dc.subject | 二極體 | zh_TW |
| dc.subject | 靜電放電 | zh_TW |
| dc.subject | 金屬氧化物半導體 | zh_TW |
| dc.subject | 矽控整流器 | zh_TW |
| dc.subject | 系統層級靜電放電 | zh_TW |
| dc.subject | bipolar junction transistor (BJT) | en_US |
| dc.subject | component-level ESD | en_US |
| dc.subject | diode | en_US |
| dc.subject | electrostatic discharge (ESD) | en_US |
| dc.subject | metal-oxide-semiconductor (MOS) | en_US |
| dc.subject | silicon-controlled rectifier (SCR) | en_US |
| dc.subject | system-level ESD | en_US |
| dc.title | 元件層級及系統層級之靜電放電防護設計 | zh_TW |
| dc.title | Component-Level and System-Level ESD Protection Design | en_US |