38 GHz 單邊帶混頻器與可變增益放大器設計

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隨著5G行動通訊發展,在相位陣列架構的射頻收發器中,混頻器與可變增益放大器為重要元件。而CMOS具有高整合度、低功率消耗、及低成本的優勢,因此本論文使用標準 65nm CMOS 1P9M製程,實現38 GHz單邊帶混頻器與可變增益放大器。第一個電路為38 GHz單邊帶混頻器,藉由準確的饋入兩顆混頻器正交訊號,將兩個相差180°的輸出訊號合成後,達到寬頻鏡像抑制之功能。當電晶體偏壓為0.4 V,頻帶為31 ~ 40 GHz,增益範圍為-19.8 ± 0.5 dB,鏡像抑制在40 dB的範圍為35~ 40 GHz,整體晶片佈局面積為0.72 mm × 0.8 mm。第二個電路為38 GHz低相位變化之可變增益放大器,採用兩級的電流控制架構,透過數位控制與相位補償技術來維持低相位變化,並加入基極偏壓來提升可變增益範圍。當供應電壓Vdd為1.2 V,在38 GHz有最高增益14.84 dB,可變增益範圍則有14.76 dB,相位誤差為4.62°,整體功率消耗約為20.4 mW,整體晶片佈局面積為0.46 mm × 0.68 mm。
As the progress of the 5th Generation Wireless System, mixers and variable gain amplifiers(VGA) play an important part in the phased-array radio frequency transceiver. Using the CMOS process has the advantages of high integration, low power consumption, and low cost. In this paper, 38 GHz single-sideband mixer (SSB Mixer) and VGA are presented, and implemented in standard 65nm CMOS technology.First, a 38 GHz SSB Mixer has designed and implemented. By accurately feeding two quadrature signals to mixers, two output signals with 180° phase difference will be synthesized for a wideband image suppresion function. When the synthesizingbias is 0.4 V, the gain range is -19.8 ± 0.5 dB from 31 to 40 GHz and the Image Rejection from 35 to 40 GHz is 40 dB. Overall chip size is 0.72 mm × 0.8 mm.Second, a 38 GHz low phase variation VGA has designed and implemented. The circuit adopted two current steering stages. We utilized digital control and phase compensation techniques to maintain low phase variations, and using body bias to increase gain control range. When the supply voltage is 1.2 V, the VGA has a peak gain of 14.84 dB at 38 GHz. The gain control range is 14.76 dB, and the phase error is 4.62°. The DC power consumption is 20.4 mW, and the chip size is 0.46 mm × 0.68 mm.



互補式金氧半導體製程, 單邊帶混頻器, 鏡像抑制, 可變增益放大器, 電流控制架構, 基極偏壓, Complementary Metal Oxide Semiconductor (CMOS), Single-Sideband Mixer (SSB Mixer), Image Rejection Ratio (IRR), Variable Gain Amplifier (VGA), Current Steering, Body Bias