Please use this identifier to cite or link to this item: http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/95836
Title: V 頻帶CMOS低雜訊放大器設計與分析
Design and Analysis of V Band CMOS Low Noise Amplifier
Authors: 蔡政翰
Jeng-Han Tsai
林益璋
Yi-Jhang Lin
Keywords: 低雜訊放大器
收發機
雜訊指數
疊接組態
V 頻段
CMOS
low noise amplifier
transceiver
Noise Figure
Cascode
MMW
CMOS
Issue Date: 2011
Abstract: 隨著無線通訊技術快速發展,射頻積體電路朝向更高頻率、更高資料傳輸速率、更寬頻帶與高整合度發展。無需執照的60GHz頻段之數GHz頻寬逹成超高速率傳輸的可行性。在60GHz前端收發機中低雜訊放大器為其中一重要元件,低雜訊放大器被用來放大從天線接收之微弱訊號且具最小雜訊指數。我們採用CMOS製程技術製作,因CMOS製程技術具有小面積、低成本、低功率消耗與高整合度等優點,在毫米波頻段是極具吸引力的製程技術。 在本論文中設計二種符合V頻段規範CMOS低雜訊放大器,所採用製程為TSMC 90nm RF CMOS process。在第一個晶片我們實現V頻帶三級串接低雜訊放大器,第一級與第二級採用雜訊指數較低之共源級組態以降低整體放大器雜訊指數,第三級則採用疊接組態以提升增益,因此,此設計在55.5GHz時有5.4dB的雜訊指數有不錯的表現,包含測試pad之晶片面積為0.46mm2,且在56.6GHz有最大增益13.1dB。 在第二個晶片設計採用二級串接疊接組態架構,我們所提出疊接組態設計方法與傳統疊接組態設計方法相比,改善了穩定度、更低雜訊指數、更高的增益與更低功率消耗,雙級串接疊接組態放大器在56.9GHz達成18.95dB峰值增益,在65.5GHz有4.7dB雜訊指數,3dB頻寬範圍從54.7GHz到63.1GHz,當頻率為60GHz時IP1dB為-20dBm,整體功率消耗為15.3mW,包含pad之晶片面積為0.308mm2。
With the rapid development of the wireless communication technologies, radio frequency integrated circuit tends to higher frequency, higher data rate, wider bandwidth and higher integration. Unlicensed multi-GHz bandwidth around 60GHz makes very high data rate transmission feasible. The low noise amplifier (LNA) is one of the most important components in the 60GHz front-end transceiver. The low noise amplifier contributes to minimum noise figure when amplifying the weak signal from the antenna. We adopt CMOS technology. It has the advantages of small size, low cost, low power consumption, and high level of integration, all of which are attractive for MMW applications. In this thesis, tow CMOS low noise amplifiers were designed for V band specifications. They are fabricated in TSMC 90nm RF CMOS process. The first chip, we present a V-band 3-stage LNA that the first and second stages utilizes the common source topology for reduce noise figure and The third stage is adopted cascode topology to boost gain. Therefore our LNA achieves excellent noise figure of 5.4dB at 55.5GHz, with miniature chip size of 0.46 mm2 including testing pads. The maximum gain is 13.1dB at 56.6GHz. The second chip, employs a 2-stage cascode topology. Compared with conventional cascode device design, the cascode device design we proposed has improved stability, lowered noise figure, contributed to higher gain and consumed lower power. The 2-stage LNA, which achieves a peak gain of 18.95dB at 56.9GHz, a noise figure of 4.7dB at 65.5GHz, a 3dB frequency bandwidth ranging from 54.7 to 63.1 GHz, an input 1dB compression point of -20dBm at 60GHz. Also the LNA consumes only 15.3mW. The total LNA die area with pads is 0.308 mm2.
URI: http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=%22http://etds.lib.ntnu.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=id=%22GN0698750279%22.&%22.id.&
http://rportal.lib.ntnu.edu.tw:80/handle/20.500.12235/95836
Other Identifiers: GN0698750279
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