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Title: An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process
Authors: 國立臺灣師範大學應用電子科技學系
Yu-Hsuan Lin
Jeng-Han Tsai
Yen-Hung Kuo
Tian-Wei Huang
Issue Date: 8-Dec-2011
Abstract: A 24 GHz 29.8 mW Phase-lock-loop using 0.18 μm CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm2 without off-chip loop filter.
Other Identifiers: ntnulib_tp_E0611_02_002
Appears in Collections:教師著作

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