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Title: 具數位校正電路之低電壓三角積分調變器設計
Authors: 國立臺灣師範大學電機工程學系
Issue Date: 31-Jul-2009
Publisher: 行政院國家科學委員會
Abstract: 隨著積體電路製程技術不斷的演進,積體電路的操作電壓持續地下 降,數位電路的速度及性能也不斷的提升。然而,由於元件的臨界電壓並 沒有隨著供應電壓等比例的降低,因此造成電晶體過趨動電壓的不足,進 而影響類比數位轉換電路的特性表現。在晶片系統(System-on-Chip, SoC) 的前提下,如何提升類比數位轉換器在低電壓操作下性能,便成為現在相 當重要的課題。 三角積分調變器技術由於其超取樣的特性,使得它非常適合用來實現 高解析度、高準確度的類比數位轉換器,我們可以在無線通信及需要高解 析的積體電路上發現它的很多應用。在本計劃的研究中,即是要利用在低 電壓操作的三角積分調變器,完成類比數位轉換器的功能。然而,低電壓 造成過趨動電壓不足,勢必造成性能的大幅下降。因此,本計劃主要目標 是結合數位校正電路的技術,來提高低電壓類比數位轉換器的性能。研究 步驟包含以下三個步驟: (1) 第一部份,分析類比電路的非理想特性在三角積分調變器中的影響, 最主要是指類比電路中的線性誤差部份。根據這些結果,提出數位方 式校正性能的演算法,以補償類比元件性能的不足,並由MATLAB驗 證此電路的可行性及最佳化,以達到高解析的目標。 (2) 第二部份電路的設計,以CMOS設計出符合音頻應用且操作在0.8V以下 的開關式運算放大器,接著結合量化器電路,以實現一個低電壓操作 的三角積分調變器。 (3) 第三部份根據所提出的演算法,以數位信號處理的方式實現類比校正 補償電路,並接著結合低電壓三角積分調變器,以期能有效提高類比 數位轉換時的解析度,並符合低電壓、高性能應用上的需求。
The supply voltage of the integrated circuits continues descending with the progress of technology so that the operational speed and performance of the digital integrated circuits are promoted. However, since the threshold voltage is not reduced proportional to the supply voltage, it reduces the required overdrive of transistors in analog circuitries. It significantly impacts the performance of the low-voltage analog-to-digital converters (ADCs) so that a strong aspiration is inspired to improve it in the modern SoC era. Delta-sigma (ΔΣ) modulators are very suitable for the realization of high resolution and high accuracy analog-to-digital converters due to its oversampling nature. It can also be found in many wireless communication applications. In this research, a ΔΣ modulator will be combined with the proposed digital correction circuits to promote the performance of the ADC operated in the low-voltage circumstance. To accomplish this research, three processes are planned as follows: (1) In the first part, explore the effect the nonidealities of the analog devices to the ΔΣ modulators, and propose an algorithm to compensate these nonidealities on analog devices to improve the performance of whole system. Verify the feasibility of the proposed algorithm and determine the optimal results by MATLAB to achieve a high resolution of ADC. (2) In the second part, we will develop a CMOS switched-opamp (SOP) that can be operated under a supply voltage of 0.8V or smaller. Then, by combining with a new low-voltage multibit quantizer and the designed SOP a new ΔΣ modulator will be proposed for the audio application. (3) In the third part, based on the proposed algorithm the digital calibration circuit will be implemented in digital form. Then, apply the developed digital correction circuit to the low-voltage ΔΣ modulator to improve the performance of the modulator.
Other Identifiers: ntnulib_tp_E0610_04_010
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